CSRNG Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	32.476us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	78.164us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	111.330us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	1.037ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	18.000s	1.047ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	381.085us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	111.330us	20	20	100.00
		csrng_csr_aliasing	18.000s	1.047ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	24.000s	1.400ms	200	200	100.00
V2	alerts	csrng_alert	1.250m	6.420ms	500	500	100.00
V2	err	csrng_err	8.000s	26.749us	500	500	100.00
V2	cmds	csrng_cmds	11.300m	73.875ms	50	50	100.00
V2	life cycle	csrng_cmds	11.300m	73.875ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.917m	120.316ms	47	50	94.00
V2	intr_test	csrng_intr_test	6.000s	94.567us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	193.830us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	996.708us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	996.708us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	78.164us	5	5	100.00
		csrng_csr_rw	6.000s	111.330us	20	20	100.00
		csrng_csr_aliasing	18.000s	1.047ms	5	5	100.00
		csrng_same_csr_outstanding	8.000s	226.857us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	78.164us	5	5	100.00
		csrng_csr_rw	6.000s	111.330us	20	20	100.00
		csrng_csr_aliasing	18.000s	1.047ms	5	5	100.00
		csrng_same_csr_outstanding	8.000s	226.857us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	9.000s	125.157us	5	5	100.00
		csrng_tl_intg_err	14.000s	1.036ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	19.368us	50	50	100.00
		csrng_csr_rw	6.000s	111.330us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.250m	6.420ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.917m	120.316ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.250m	6.420ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.917m	120.316ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.250m	6.420ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	1.036ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
		csrng_sec_cm	9.000s	125.157us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	24.000s	1.400ms	200	200	100.00
		csrng_err	8.000s	26.749us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.783m	5.634ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.76	98.61	96.62	99.94	97.42	92.02	100.00	97.17	91.03

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.97611578480682735962519932258009119551999805205688107934684968505549933660231
      Line 101, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3280571278 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3280571278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.113421755659519697179633336650894124501713133577403264445170918418740225945240
      Line 100, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 613164956 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 613164956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 14.csrng_stress_all.8372843007705138414006218582514817545443728025982955231039674500699281040324
      Line 155, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log

        UVM_ERROR @ 2797777425 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 2797777425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 37.csrng_stress_all.17076173121930803416617853247761030294379826386906645418495064908279618395893
      Line 135, in log /nightly/runs/scratch/dj-sw-nightly/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log

        UVM_ERROR @  34573886 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  34573886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.