DMA Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	12.000s	3.422ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	12.000s	569.344us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	13.000s	789.157us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	109.435us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	54.421us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	15.000s	13.457ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	10.000s	2.531ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	25.386us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	54.421us	20	20	100.00
		dma_csr_aliasing	10.000s	2.531ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.967m	6.100ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	52.750m	275.389ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	14.183m	70.705ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	53.633m	1.106s	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	52.750m	275.389ms	3	3	100.00
V2	dma_abort	dma_abort	20.000s	13.721ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	2.917m	10.056ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	11.627us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	125.431us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	125.431us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	109.435us	5	5	100.00
		dma_csr_rw	5.000s	54.421us	20	20	100.00
		dma_csr_aliasing	10.000s	2.531ms	5	5	100.00
		dma_same_csr_outstanding	6.000s	156.752us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	109.435us	5	5	100.00
		dma_csr_rw	5.000s	54.421us	20	20	100.00
		dma_csr_aliasing	10.000s	2.531ms	5	5	100.00
		dma_same_csr_outstanding	6.000s	156.752us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	39.000s	370.385us	5	5	100.00
		dma_generic_stress	53.633m	1.106s	5	5	100.00
		dma_handshake_stress	52.750m	275.389ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	1.059ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.367m	33.651ms	5	5	100.00
		dma_longer_transfer	28.000s	1.207ms	4	5	80.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
76.34	97.08	95.25	97.04	96.57	84.02	82.76	97.86	41.99

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_longer_transfer has 1 failures.

    • 2.dma_longer_transfer.36427791237327721413176721166835187439311508390517209707678809906477809307502
      Log /nightly/runs/scratch/dj-sw-nightly/dma-sim-xcelium/2.dma_longer_transfer/latest/run.log

        Job timed out after 60 minutes