EDN Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.960s 68.435us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.080s 36.274us 5 5 100.00
V1 csr_rw edn_csr_rw 2.250s 32.367us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.660s 255.151us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.670s 144.814us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.610s 41.018us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.250s 32.367us 20 20 100.00
edn_csr_aliasing 2.670s 144.814us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.860s 785.383us 300 300 100.00
V2 csrng_commands edn_genbits 6.860s 785.383us 300 300 100.00
V2 genbits edn_genbits 6.860s 785.383us 300 300 100.00
V2 interrupts edn_intr 2.990s 26.782us 50 50 100.00
V2 alerts edn_alert 3.270s 32.639us 200 200 100.00
V2 errs edn_err 3.100s 28.565us 100 100 100.00
V2 disable edn_disable 2.910s 41.162us 50 50 100.00
edn_disable_auto_req_mode 3.110s 121.357us 50 50 100.00
V2 stress_all edn_stress_all 7.860s 439.061us 50 50 100.00
V2 intr_test edn_intr_test 2.270s 23.675us 50 50 100.00
V2 alert_test edn_alert_test 2.950s 43.012us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.870s 328.425us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.870s 328.425us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.080s 36.274us 5 5 100.00
edn_csr_rw 2.250s 32.367us 20 20 100.00
edn_csr_aliasing 2.670s 144.814us 5 5 100.00
edn_same_csr_outstanding 2.450s 40.928us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.080s 36.274us 5 5 100.00
edn_csr_rw 2.250s 32.367us 20 20 100.00
edn_csr_aliasing 2.670s 144.814us 5 5 100.00
edn_same_csr_outstanding 2.450s 40.928us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 10.180s 957.200us 5 5 100.00
edn_tl_intg_err 4.960s 272.323us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.700s 84.566us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.270s 32.639us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.180s 957.200us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.180s 957.200us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 10.180s 957.200us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.180s 957.200us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.270s 32.639us 200 200 100.00
edn_sec_cm 10.180s 957.200us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.270s 32.639us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.960s 272.323us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.506m 9.738ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 1108 1130 98.05

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.92 98.32 94.23 97.02 92.44 96.33 99.78 93.32

Failure Buckets