HMAC Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.630s	10.590ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.330s	73.251us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.250s	243.289us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.490s	6.552ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.250s	368.374us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	9.683m	182.368ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.250s	243.289us	20	20	100.00
		hmac_csr_aliasing	8.250s	368.374us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.858m	11.628ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.779m	1.635ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.400m	13.676ms	30	30	100.00
		hmac_test_sha384_vectors	6.624m	12.638ms	75	75	100.00
		hmac_test_sha512_vectors	6.765m	11.373ms	75	75	100.00
		hmac_test_hmac256_vectors	13.380s	4.250ms	50	50	100.00
		hmac_test_hmac384_vectors	14.670s	986.329us	60	60	100.00
		hmac_test_hmac512_vectors	16.320s	321.100us	75	75	100.00
V2	burst_wr	hmac_burst_wr	39.610s	12.174ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	22.622m	78.838ms	50	50	100.00
V2	error	hmac_error	2.287m	14.023ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.343m	11.538ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.630s	10.590ms	50	50	100.00
		hmac_long_msg	1.858m	11.628ms	50	50	100.00
		hmac_back_pressure	1.779m	1.635ms	50	50	100.00
		hmac_datapath_stress	22.622m	78.838ms	50	50	100.00
		hmac_burst_wr	39.610s	12.174ms	50	50	100.00
		hmac_stress_all	47.628m	241.461ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.630s	10.590ms	50	50	100.00
		hmac_long_msg	1.858m	11.628ms	50	50	100.00
		hmac_back_pressure	1.779m	1.635ms	50	50	100.00
		hmac_datapath_stress	22.622m	78.838ms	50	50	100.00
		hmac_wipe_secret	2.343m	11.538ms	50	50	100.00
		hmac_test_sha256_vectors	4.400m	13.676ms	30	30	100.00
		hmac_test_sha384_vectors	6.624m	12.638ms	75	75	100.00
		hmac_test_sha512_vectors	6.765m	11.373ms	75	75	100.00
		hmac_test_hmac256_vectors	13.380s	4.250ms	50	50	100.00
		hmac_test_hmac384_vectors	14.670s	986.329us	60	60	100.00
		hmac_test_hmac512_vectors	16.320s	321.100us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.630s	10.590ms	50	50	100.00
		hmac_long_msg	1.858m	11.628ms	50	50	100.00
		hmac_back_pressure	1.779m	1.635ms	50	50	100.00
		hmac_datapath_stress	22.622m	78.838ms	50	50	100.00
		hmac_burst_wr	39.610s	12.174ms	50	50	100.00
		hmac_error	2.287m	14.023ms	50	50	100.00
		hmac_wipe_secret	2.343m	11.538ms	50	50	100.00
		hmac_test_sha256_vectors	4.400m	13.676ms	30	30	100.00
		hmac_test_sha384_vectors	6.624m	12.638ms	75	75	100.00
		hmac_test_sha512_vectors	6.765m	11.373ms	75	75	100.00
		hmac_test_hmac256_vectors	13.380s	4.250ms	50	50	100.00
		hmac_test_hmac384_vectors	14.670s	986.329us	60	60	100.00
		hmac_test_hmac512_vectors	16.320s	321.100us	75	75	100.00
		hmac_stress_all	47.628m	241.461ms	50	50	100.00
V2	stress_all	hmac_stress_all	47.628m	241.461ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.080s	18.384us	50	50	100.00
V2	intr_test	hmac_intr_test	2.140s	13.639us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.280s	621.200us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.280s	621.200us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.330s	73.251us	5	5	100.00
		hmac_csr_rw	2.250s	243.289us	20	20	100.00
		hmac_csr_aliasing	8.250s	368.374us	5	5	100.00
		hmac_same_csr_outstanding	3.790s	668.670us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.330s	73.251us	5	5	100.00
		hmac_csr_rw	2.250s	243.289us	20	20	100.00
		hmac_csr_aliasing	8.250s	368.374us	5	5	100.00
		hmac_same_csr_outstanding	3.790s	668.670us	20	20	100.00
V2		TOTAL			855	855	100.00
V2S	tl_intg_err	hmac_sec_cm	2.600s	650.549us	5	5	100.00
		hmac_tl_intg_err	5.580s	231.397us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.580s	231.397us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.630s	10.590ms	50	50	100.00
V3	stress_reset	hmac_stress_reset	8.420s	510.506us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	5.958m	4.919ms	25	25	100.00
V3		TOTAL			75	75	100.00
	Unmapped tests	hmac_directed	2.590s	12.916us	1	1	100.00
		TOTAL			1061	1061	100.00

Failure Buckets

• Job returned non-zero exit code has 1 failures:
  • Test hmac has 1 failures.

    • cov_report
      Log /nightly/runs/scratch/dj-sw-nightly/hmac-sim-vcs/cov_report/cov_report.log

        Grading tests: .
      
        Error-[URG-GLF] Test load failed
          You specified the '-grade' option to URG, but grading failed: Could not load
          exclude file /nightly/runs/opentitan/hw/ip/hmac/dv/cov/hmac_cov_excl.el.
          The test may have been corrupted. Please try regenerating it. If the problem
          still persists, please contact vcs_support@synopsys.com.
      
      
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:241: cov_report] Error 1