I2C Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.402m	7.458ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	49.930s	9.078ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.240s	26.890us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.310s	83.796us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.950s	422.222us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.190s	296.466us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.520s	33.950us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.310s	83.796us	20	20	100.00
		i2c_csr_aliasing	3.190s	296.466us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	27.454m	600.000ms	47	50	94.00
V2	host_stress_all	i2c_host_stress_all	26.845m	163.777ms	14	50	28.00
V2	host_maxperf	i2c_host_perf	25.340m	49.739ms	49	50	98.00
V2	host_override	i2c_host_override	2.280s	19.677us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.992m	84.668ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.541m	2.625ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.890s	110.183us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.900s	540.414us	50	50	100.00
		i2c_host_fifo_reset_rx	14.310s	525.136us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.682m	7.940ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	45.940s	1.429ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.940s	305.947us	13	50	26.00
V2	target_glitch	i2c_target_glitch	14.910s	21.914ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	19.195m	103.946ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	8.870s	956.207us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.049m	1.808ms	50	50	100.00
		i2c_target_intr_smoke	13.290s	7.069ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.750s	1.169ms	50	50	100.00
		i2c_target_fifo_reset_tx	3.390s	266.373us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	27.130m	71.061ms	50	50	100.00
		i2c_target_stress_rd	1.049m	1.808ms	50	50	100.00
		i2c_target_intr_stress_wr	7.445m	25.002ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.710s	1.524ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.811m	4.146ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	9.940s	4.998ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	46.650s	10.235ms	19	50	38.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.360s	3.021ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.240s	146.598us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	25.340m	49.739ms	49	50	98.00
		i2c_host_perf_precise	16.132m	23.217ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	45.940s	1.429ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	43.540s	2.869ms	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.550s	752.026us	50	50	100.00
		i2c_target_nack_acqfull_addr	4.930s	546.283us	50	50	100.00
		i2c_target_nack_txstretch	3.420s	133.264us	35	50	70.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	28.700s	1.276ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.520s	518.276us	50	50	100.00
V2	alert_test	i2c_alert_test	2.250s	16.910us	50	50	100.00
V2	intr_test	i2c_intr_test	2.330s	29.849us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.920s	147.416us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.920s	147.416us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.240s	26.890us	5	5	100.00
		i2c_csr_rw	2.310s	83.796us	20	20	100.00
		i2c_csr_aliasing	3.190s	296.466us	5	5	100.00
		i2c_same_csr_outstanding	2.650s	62.360us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.240s	26.890us	5	5	100.00
		i2c_csr_rw	2.310s	83.796us	20	20	100.00
		i2c_csr_aliasing	3.190s	296.466us	5	5	100.00
		i2c_same_csr_outstanding	2.650s	62.360us	20	20	100.00
V2		TOTAL			1658	1792	92.52
V2S	tl_intg_err	i2c_tl_intg_err	3.700s	923.804us	20	20	100.00
		i2c_sec_cm	2.740s	191.652us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.700s	923.804us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	52.760s	1.873ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.050s	703.624us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	41.670s	4.973ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1838	2042	90.01

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.25	97.44	89.97	74.17	73.21	94.46	98.51	89.96

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 47 failures:

Test i2c_host_mode_toggle has 20 failures.

0.i2c_host_mode_toggle.38281146568784980788527095856704157571500390935728604076330876503423254507886
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  74364932 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13109

1.i2c_host_mode_toggle.111853813311865463977709888380328600476824867111821446699611470752572177525205
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 118977830 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @109631

... and 18 more failures.

Test i2c_host_stress_all has 27 failures.

1.i2c_host_stress_all.97904609090468813555510993530205624952249451591087370825134239737687072787387
Line 186, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 47457992360 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8745416

4.i2c_host_stress_all.93826721057314862493644598288516616682848342757896109589762817835309773859353
Line 129, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 26290100797 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4468304

... and 25 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 31 failures:
- Test i2c_target_hrst has 31 failures.
  - 0.i2c_target_hrst.88210988686052523366548845539293497963572639083303316413182777856955738773071
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10240198812 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10240198812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_hrst.105029634778382660503566875938817186148090374850670930816177819853348791484538
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10398754101 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10398754101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 29 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 24 failures:
- Test i2c_target_unexp_stop has 24 failures.
  - 0.i2c_target_unexp_stop.88349731787344352048996017053793963833639390248342312396494647081032052121583
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 114239468 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 53 [0x35])
  UVM_INFO @ 114239468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.2032690653157297343277537512119711800001729138176556031782128103288486416418
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 131585487 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 189 [0xbd])
  UVM_INFO @ 131585487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 18 failures:
- Test i2c_target_unexp_stop has 18 failures.
  - 2.i2c_target_unexp_stop.73360792303545308978102656245020249307804444042809757913826704725217760395292
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 154473661 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 154473661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.33045910103940251926001642569510527246115575516629288575690337478338623792501
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  64458906 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  64458906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.111259823974258956452450944119340088977564402191917128683555046227628391097235
Line 105, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8778927249 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8778927249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.79955659571398203975794623914362737387361566296003194458397391764696776896233
Line 80, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 186211674 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 186211674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

0.i2c_target_stress_all_with_rand_reset.40512579612106738821875662819216940154824869410587324638212779484937651743661
Line 134, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1977518730 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1977518730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.98910497680017116267934176501008591008514548452709174329986927033692441171094
Line 95, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4972772772 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4972772772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
- Test i2c_target_nack_txstretch has 15 failures.
  - 0.i2c_target_nack_txstretch.102059979927285886306022206418860448839133145958134354965245409576327074055521
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 906397577 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 906397577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_nack_txstretch.1835875159314778134339919933619565446348614857480966023367105441400233303697
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 154394793 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 154394793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 12 failures.

2.i2c_host_mode_toggle.84951251951764757947328687300148522591535165142815629005422351877786566371931
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 143365223 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

9.i2c_host_mode_toggle.110839902364067103960773498609751865888424114112706914250611565301360065573963
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  39412077 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

Test i2c_host_stress_all has 1 failures.

24.i2c_host_stress_all.63676048014516870165541494839012861912383877143382550582795170339497804245797
Line 128, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 134981740462 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:

Test i2c_target_unexp_stop has 8 failures.

1.i2c_target_unexp_stop.41158143875137912603058426971875357374305106330412737246966756489826029936820
Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 104494638 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 104494638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.i2c_target_unexp_stop.114103399141412762543813806277405564255211262759975041167621643602742518207743
Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 128965042 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 128965042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
- Test i2c_target_stretch has 7 failures.
  - 6.i2c_target_stretch.114061173099267673020580206255504428381730523787925007894766178883651792979285
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10025099175 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10025099175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.i2c_target_stretch.115108120737728133160976647733934304824493392635857619808794866459825924291835
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011187915 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011187915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
- Test i2c_host_mode_toggle has 5 failures.
  - 14.i2c_host_mode_toggle.19078727021058210059876909723351730169793377858772349343589408762722282673872
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  40821824 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x2e6b994, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  40821824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.i2c_host_mode_toggle.71045797192108255479645253669153815288552495022624473736676322170678987278761
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 102305534 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xa721694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 102305534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:

Test i2c_host_stress_all has 4 failures.

0.i2c_host_stress_all.64909023082429795636769598489921217697240076678524290298070713363189805690399
Line 124, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 14263124376 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2051272

7.i2c_host_stress_all.94042000009022858009705716229101674865866368854994811152134167196091141521320
Line 185, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 13807555526 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @598010

... and 2 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 31.i2c_target_tx_stretch_ctrl.34132445353829621366970875616910800297413120327193424827229063588557781122999
    Line 119, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 42.i2c_target_tx_stretch_ctrl.63672179651523105440113625119706522709568474895422829319827210140287600714965
    Line 119, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:794) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 1.i2c_target_stress_all_with_rand_reset.73773813533871900557939071337853042815452731912611181663805109077112968048098
    Line 82, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 394308576 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 394308576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_stress_all_with_rand_reset.36061149366544110059815410487266560820467955344985154764287450892263440749087
    Line 78, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 193422602 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 193422602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 3 failures:
- Test i2c_host_stress_all has 2 failures.
  - 3.i2c_host_stress_all.84333878937644839397222365192710871676890044359730700039943481715808212922028
    Log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 46.i2c_host_stress_all.110199941120446566116102388011769580736161188298152239486530590039727260466870
    Log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/46.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_error_intr has 1 failures.
  - 29.i2c_host_error_intr.69630148995274520432109863306909683398103030065580898477982643502351744951369
    Log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/29.i2c_host_error_intr/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test i2c_host_error_intr has 1 failures.
  - 26.i2c_host_error_intr.47564387213802510116825868799353149124964491514464198004562488708165474899408
    Line 103, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/26.i2c_host_error_intr/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_stress_all has 1 failures.
  - 48.i2c_host_stress_all.88428124041103568876308937567756424848586289800452896788555805886875650156389
    Line 175, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/48.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=71) has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 3.i2c_host_perf.8766354970584867937446011101495953095180589448348498451138456961382306003261
    Line 75, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 10096147294 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0xb0df1c94, Comparison=CompareOpEq, exp_data=0x0, call_count=71)
  UVM_INFO @ 10096147294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_error_intr has 1 failures.
  - 3.i2c_host_error_intr.36442851572193620107267598835986082507947363571320087967574491121288100377108
    Line 121, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/3.i2c_host_error_intr/latest/run.log
```
  UVM_ERROR @ 115661733 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_target_stress_all_with_rand_reset.53258316185344724331120575985788921555218009885440257032333998882042101061551
    Line 91, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  15577018 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @  15577018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 17.i2c_host_stress_all.5813793302601575010189841622787492624326421794997805333527978510942941615343
    Line 92, in log /nightly/runs/scratch/dj-sw-nightly/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @  63250744 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (0 [0x0] vs 3 [0x3])
  UVM_INFO @  63250744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```