KEYMGR Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 17.690s 3.482ms 49 50 98.00
V1 random keymgr_random 45.450s 1.937ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 4.090s 236.799us 5 5 100.00
V1 csr_rw keymgr_csr_rw 3.770s 12.845us 17 20 85.00
V1 csr_bit_bash keymgr_csr_bit_bash 11.210s 1.007ms 4 5 80.00
V1 csr_aliasing keymgr_csr_aliasing 8.450s 135.835us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 4.860s 147.675us 15 20 75.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 3.770s 12.845us 17 20 85.00
keymgr_csr_aliasing 8.450s 135.835us 5 5 100.00
V1 TOTAL 145 155 93.55
V2 cfgen_during_op keymgr_cfg_regwen 38.490s 1.031ms 47 50 94.00
V2 sideload keymgr_sideload 27.590s 2.046ms 50 50 100.00
keymgr_sideload_kmac 27.680s 3.618ms 50 50 100.00
keymgr_sideload_aes 33.040s 1.696ms 49 50 98.00
keymgr_sideload_otbn 41.320s 17.883ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 25.340s 16.037ms 49 50 98.00
V2 lc_disable keymgr_lc_disable 20.910s 1.069ms 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 10.010s 2.443ms 37 50 74.00
V2 invalid_sw_input keymgr_sw_invalid_input 42.700s 9.360ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 28.100s 5.866ms 49 50 98.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 16.720s 7.491ms 39 50 78.00
V2 stress_all keymgr_stress_all 5.785m 37.809ms 44 50 88.00
V2 intr_test keymgr_intr_test 3.810s 38.027us 50 50 100.00
V2 alert_test keymgr_alert_test 2.910s 10.782us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 6.310s 2.011ms 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 6.310s 2.011ms 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 4.090s 236.799us 5 5 100.00
keymgr_csr_rw 3.770s 12.845us 17 20 85.00
keymgr_csr_aliasing 8.450s 135.835us 5 5 100.00
keymgr_same_csr_outstanding 5.270s 89.219us 14 20 70.00
V2 tl_d_partial_access keymgr_csr_hw_reset 4.090s 236.799us 5 5 100.00
keymgr_csr_rw 3.770s 12.845us 17 20 85.00
keymgr_csr_aliasing 8.450s 135.835us 5 5 100.00
keymgr_same_csr_outstanding 5.270s 89.219us 14 20 70.00
V2 TOTAL 698 740 94.32
V2S sec_cm_additional_check keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
keymgr_tl_intg_err 7.990s 941.415us 12 20 60.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 5.580s 179.191us 2 20 10.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 5.580s 179.191us 2 20 10.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 5.580s 179.191us 2 20 10.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 5.580s 179.191us 2 20 10.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 8.590s 213.393us 2 20 10.00
V2S prim_count_check keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 7.990s 941.415us 12 20 60.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 5.580s 179.191us 2 20 10.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 38.490s 1.031ms 47 50 94.00
V2S sec_cm_reseed_config_regwen keymgr_random 45.450s 1.937ms 50 50 100.00
keymgr_csr_rw 3.770s 12.845us 17 20 85.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 45.450s 1.937ms 50 50 100.00
keymgr_csr_rw 3.770s 12.845us 17 20 85.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 45.450s 1.937ms 50 50 100.00
keymgr_csr_rw 3.770s 12.845us 17 20 85.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 20.910s 1.069ms 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 28.100s 5.866ms 49 50 98.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 28.100s 5.866ms 49 50 98.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 45.450s 1.937ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 30.220s 4.406ms 49 50 98.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 35.870s 1.684ms 35 50 70.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 20.910s 1.069ms 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 35.870s 1.684ms 35 50 70.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 35.870s 1.684ms 35 50 70.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 35.870s 1.684ms 35 50 70.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 9.490s 2.185ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 35.870s 1.684ms 35 50 70.00
V2S TOTAL 105 165 63.64
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 18.870s 700.543us 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 978 1110 88.11

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.67 99.10 97.51 98.26 100.00 99.01 98.61 91.18

Failure Buckets