KMAC/MASKED Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.532m	17.227ms	47	50	94.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.570s	33.008us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.630s	50.778us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.210s	1.670ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.450s	1.471ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.140s	143.009us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.630s	50.778us	20	20	100.00
		kmac_csr_aliasing	9.450s	1.471ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.230s	149.830us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.990s	41.202us	5	5	100.00
V1		TOTAL			112	115	97.39
V2	long_msg_and_output	kmac_long_msg_and_output	58.504m	282.973ms	50	50	100.00
V2	burst_write	kmac_burst_write	21.770m	178.387ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.931m	64.484ms	5	5	100.00
		kmac_test_vectors_sha3_256	32.425m	87.542ms	5	5	100.00
		kmac_test_vectors_sha3_384	20.922m	13.721ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.394m	78.924ms	5	5	100.00
		kmac_test_vectors_shake_128	34.909m	184.942ms	5	5	100.00
		kmac_test_vectors_shake_256	27.212m	114.338ms	5	5	100.00
		kmac_test_vectors_kmac	5.740s	170.970us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.660s	317.608us	5	5	100.00
V2	sideload	kmac_sideload	8.904m	89.014ms	50	50	100.00
V2	app	kmac_app	6.556m	52.133ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.020m	6.229ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.223m	15.205ms	50	50	100.00
V2	error	kmac_error	7.157m	28.342ms	50	50	100.00
V2	key_error	kmac_key_error	21.740s	9.628ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.810s	471.612us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.210s	5.033ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	7.690s	137.403us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.664m	56.636ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	49.520s	1.921ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.277m	180.456ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.390s	17.058us	50	50	100.00
V2	alert_test	kmac_alert_test	3.880s	21.837us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.730s	150.594us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.730s	150.594us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.570s	33.008us	5	5	100.00
		kmac_csr_rw	2.630s	50.778us	20	20	100.00
		kmac_csr_aliasing	9.450s	1.471ms	5	5	100.00
		kmac_same_csr_outstanding	4.310s	1.717ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.570s	33.008us	5	5	100.00
		kmac_csr_rw	2.630s	50.778us	20	20	100.00
		kmac_csr_aliasing	9.450s	1.471ms	5	5	100.00
		kmac_same_csr_outstanding	4.310s	1.717ms	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.120s	68.342us	5	20	25.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.120s	68.342us	5	20	25.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.120s	68.342us	5	20	25.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.120s	68.342us	5	20	25.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.290s	77.018us	6	20	30.00
V2S	tl_intg_err	kmac_sec_cm	59.860s	4.972ms	5	5	100.00
		kmac_tl_intg_err	6.160s	760.445us	10	20	50.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.160s	760.445us	10	20	50.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	49.520s	1.921ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.532m	17.227ms	47	50	94.00
V2S	sec_cm_key_sideload	kmac_sideload	8.904m	89.014ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.120s	68.342us	5	20	25.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	59.860s	4.972ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	59.860s	4.972ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	59.860s	4.972ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.532m	17.227ms	47	50	94.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	49.520s	1.921ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	59.860s	4.972ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.941m	70.137ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.532m	17.227ms	47	50	94.00
V2S		TOTAL			36	75	48.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.870m	9.360ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			894	940	95.11

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.31	99.18	94.50	99.89	79.58	97.09	99.36	97.58

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q

has 21 failures:

Test kmac_shadow_reg_errors has 15 failures.

0.kmac_shadow_reg_errors.6010659788685283497590929880862667200935841085662897780845716838834840621325
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  65548564 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  65548564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors.33042479677265902810087040637919957861639848205969141319250790525993272474924
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  23679635 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  23679635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

5.kmac_shadow_reg_errors_with_csr_rw.80578017345831455421201766322986752092369976915104238848490005093940445006299
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  61074011 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  61074011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.48901996252148446112069552754808534117228549947205905677677266292952940675081
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @   9292264 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   9292264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 17 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

0.kmac_shadow_reg_errors_with_csr_rw.55390338387656697873294488879190886620945782670624202863611297093855310786913
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  16613936 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  16613936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.107286051270745757177102888439128173593426607882765735508767180683170385804040
Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @ 135399645 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @ 135399645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 10 failures.

2.kmac_tl_intg_err.20047856593852130679712213924791933984566563348166911689939055314211825737883
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  22240423 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  22240423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.94314729710172750863136856958964231984273567734963137606883075966202579081737
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @   8169880 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @   8169880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.63096928891628263574470937434763189852661733825061890833128194428184370929048
    Line 193, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14674678715 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 14674678715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.83421069893370060793128557891388097549859818300047764310503167923663758407572
    Line 214, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6321938185 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6321938185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_smoke has 3 failures.
  - 7.kmac_smoke.30138460164494850789723785850616741550317035866913470705846699482013950681220
    Line 72, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/7.kmac_smoke/latest/run.log
```
  UVM_ERROR @  71657225 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  71657225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.kmac_smoke.65926731190090064468664447620656305836580388643132731718834417450639783973970
    Line 72, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/13.kmac_smoke/latest/run.log
```
  UVM_ERROR @  96816130 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  96816130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:969) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 13.kmac_shadow_reg_errors_with_csr_rw.9197320413450963060987192176020140327113619454435245415233692334966076443706
    Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  33035750 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @  33035750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```