KMAC/UNMASKED Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.107m	11.647ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.650s	74.311us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.590s	48.065us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.030s	2.924ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.680s	529.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.060s	149.629us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.590s	48.065us	20	20	100.00
		kmac_csr_aliasing	8.680s	529.565us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.190s	29.681us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.720s	123.162us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.694m	100.401ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.364m	30.999ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.240m	94.308ms	5	5	100.00
		kmac_test_vectors_sha3_256	27.262m	349.004ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.731m	653.566ms	5	5	100.00
		kmac_test_vectors_sha3_512	8.792m	9.016ms	5	5	100.00
		kmac_test_vectors_shake_128	31.595m	72.579ms	5	5	100.00
		kmac_test_vectors_shake_256	30.655m	188.319ms	5	5	100.00
		kmac_test_vectors_kmac	3.590s	35.130us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.070s	208.762us	5	5	100.00
V2	sideload	kmac_sideload	6.922m	32.032ms	50	50	100.00
V2	app	kmac_app	4.064m	12.637ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.107m	8.918ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.803m	17.600ms	50	50	100.00
V2	error	kmac_error	6.162m	13.139ms	50	50	100.00
V2	key_error	kmac_key_error	14.080s	6.344ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.876m	10.170ms	37	50	74.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.090s	18.993ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.730s	17.127ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.300s	8.575ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.740s	1.235ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.493m	400.418ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.340s	45.863us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	28.127us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.680s	199.262us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.680s	199.262us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.650s	74.311us	5	5	100.00
		kmac_csr_rw	2.590s	48.065us	20	20	100.00
		kmac_csr_aliasing	8.680s	529.565us	5	5	100.00
		kmac_same_csr_outstanding	4.090s	125.259us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.650s	74.311us	5	5	100.00
		kmac_csr_rw	2.590s	48.065us	20	20	100.00
		kmac_csr_aliasing	8.680s	529.565us	5	5	100.00
		kmac_same_csr_outstanding	4.090s	125.259us	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.750s	199.636us	8	20	40.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.750s	199.636us	8	20	40.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.750s	199.636us	8	20	40.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.750s	199.636us	8	20	40.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.210s	170.567us	7	20	35.00
V2S	tl_intg_err	kmac_sec_cm	53.200s	21.250ms	5	5	100.00
		kmac_tl_intg_err	5.500s	108.381us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.500s	108.381us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.740s	1.235ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.107m	11.647ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.922m	32.032ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.750s	199.636us	8	20	40.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.200s	21.250ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.200s	21.250ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.200s	21.250ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.107m	11.647ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.740s	1.235ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.200s	21.250ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.262m	76.897ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.107m	11.647ms	50	50	100.00
V2S		TOTAL			43	75	57.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.781m	45.797ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			889	940	94.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.98	97.60	94.42	100.00	74.38	95.98	99.34	96.13

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 19 failures:

Test kmac_shadow_reg_errors has 12 failures.

1.kmac_shadow_reg_errors.75874022098891253330737885696588689592098094158575401109534247202582656933860
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  60361910 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  60361910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors.107806233503664126618282480729503980078930091250717046177072967641830620632990
Line 85, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @   3609160 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   3609160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

1.kmac_shadow_reg_errors_with_csr_rw.72409731043940766273591327820798867038361641401342020998594621398584623752943
Line 85, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  20962846 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  20962846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors_with_csr_rw.76350045280047931202779020498591622112329359697210972083913257536882506501915
Line 85, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 133717520 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 133717520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 13 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

2.kmac_shadow_reg_errors_with_csr_rw.20710073068686697883988640044149582029198938972838522776040892838727614830104
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @  23739571 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @  23739571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.9596875513220947254732002669828368792239713378415770996244179727453388659084
Line 86, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @   8658184 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @   8658184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_tl_intg_err has 7 failures.

5.kmac_tl_intg_err.9370738376884970613781356435280401931890137089660340933062977572965912565879
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  47914569 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  47914569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_tl_intg_err.61547476123711636227576853005536649529749967292407606170019075433022706318687
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  14445288 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  14445288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:890) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.74302999316672330664417822519842317542325297355158218906109657176757372438920
    Line 98, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2112386514 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2112386514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.89835782323122195392228874414354864210670165608774274489749329020742128343448
    Line 265, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6505906030 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6505906030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 6.kmac_sideload_invalid.68420986578420408838768451878672363449167512748203898056946624512543688949262
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10035028605 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9a627000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10035028605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.kmac_sideload_invalid.91149362305863124807860659794040656070470944415367034593476659900891713308386
    Line 73, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10029328327 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdf36a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10029328327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 8.kmac_sideload_invalid.73998835799354548089229811420402396786934261087809259456926501021631445818711
    Line 81, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10676618642 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb75b2000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10676618642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.kmac_sideload_invalid.11751444731819179613991502708744509496875435351763354925043237114803009610973
    Line 83, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10323920744 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2a56f000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10323920744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 11.kmac_sideload_invalid.10686649003741457811247054005193289339863573046652658005489898781363678352091
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10027397649 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7a6bf000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10027397649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.kmac_sideload_invalid.88816575086204977157915521253943824450012091633223974800435066347239582722596
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10062290620 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x596ef000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10062290620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 2.kmac_sideload_invalid.73951885217785936568513445762236875099347204318778418045929135158576926254479
    Line 88, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10106048340 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd9ec4000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10106048340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 5.kmac_stress_all_with_rand_reset.13781277557475605051199977055873547067135196302955449089769021580027895470667
    Line 156, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2957837352 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2957837352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 16.kmac_sideload_invalid.99181815894327727834336940912077707976105496323661046757237396547058652348418
    Line 89, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10409110032 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x34fc3000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10409110032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 25.kmac_sideload_invalid.78059245553241427848050417949319332724687236930197909570461468743754642398098
    Line 76, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10185011152 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3d2a1000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10185011152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 42.kmac_sideload_invalid.96980221205420940176661523554249222225532826312954772972514198778251346764788
    Line 97, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10169906866 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1e446000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
  UVM_INFO @ 10169906866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 48.kmac_sideload_invalid.78029063069078885606538445778343118309459569797703703009777253731970925155284
    Line 82, in log /nightly/runs/scratch/dj-sw-nightly/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10232777406 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc9373000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10232777406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```