RV_DM/USE_DMI_INTERFACE Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.350s	2.819us	0	2	0.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.060s	749.271ns	0	5	0.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.240s	734.680ns	0	20	0.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.140s	2.808us	0	5	0.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.100s	2.609us	0	5	0.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	2.140s	753.400ns	0	5	0.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	2.430s	1.230us	0	20	0.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.230s	976.402ns	0	20	0.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.210s	3.219us	0	5	0.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.070s	6.343us	0	2	0.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.010s	3.404us	0	2	0.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.180s	658.657ns	0	2	0.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.120s	845.204ns	0	2	0.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.180s	732.712ns	0	2	0.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.190s	3.390us	0	2	0.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	2.160s	1.422us	0	2	0.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.380s	2.216us	0	8	0.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.070s	6.343us	0	2	0.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.140s	2.722us	0	2	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.030s	1.601us	0	2	0.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.180s	658.657ns	0	2	0.00
V1	rom_read_access	rv_dm_rom_read_access	2.100s	1.686us	0	2	0.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.100s	1.658us	0	5	0.00
V1	csr_rw	rv_dm_csr_rw	2.370s	8.809us	0	20	0.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	2.200s	4.151us	0	5	0.00
V1	csr_aliasing	rv_dm_csr_aliasing	2.040s	1.762us	0	5	0.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	2.400s	757.723ns	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	2.040s	1.762us	0	5	0.00
		rv_dm_csr_rw	2.370s	8.809us	0	20	0.00
V1	mem_walk	rv_dm_mem_walk	2.160s	1.391us	0	5	0.00
V1	mem_partial_access	rv_dm_mem_partial_access	2.160s	2.344us	0	5	0.00
V1		TOTAL			0	180	0.00
V2	idcode	rv_dm_smoke	2.350s	2.819us	0	2	0.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.910s	6.070us	0	2	0.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.140s	6.885us	0	2	0.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.110s	3.464us	0	2	0.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.060s	727.488ns	0	2	0.00
V2	sba	rv_dm_sba_tl_access	3.450s	3.271us	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	3.430s	737.393ns	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	3.450s	1.426us	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.410s	3.384us	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.110s	1.073us	0	2	0.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.100s	1.747us	0	2	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.000s	5.598us	0	2	0.00
V2	hart_unavail	rv_dm_hart_unavail	2.240s	1.299us	0	5	0.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	2.200s	765.418ns	0	1	0.00
		rv_dm_tap_fsm_rand_reset	2.220s	5.416us	0	10	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.620s	1.506us	0	1	0.00
V2	stress_all	rv_dm_stress_all	3.690s	3.228us	0	50	0.00
V2	alert_test	rv_dm_alert_test	3.630s	1.905us	0	50	0.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	2.470s	600.534ns	0	20	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	2.470s	600.534ns	0	20	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	2.040s	1.762us	0	5	0.00
		rv_dm_csr_hw_reset	2.100s	1.658us	0	5	0.00
		rv_dm_csr_rw	2.370s	8.809us	0	20	0.00
		rv_dm_same_csr_outstanding	2.400s	653.930ns	0	20	0.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	2.040s	1.762us	0	5	0.00
		rv_dm_csr_hw_reset	2.100s	1.658us	0	5	0.00
		rv_dm_csr_rw	2.370s	8.809us	0	20	0.00
		rv_dm_same_csr_outstanding	2.400s	653.930ns	0	20	0.00
V2		TOTAL			0	251	0.00
V2S	tl_intg_err	rv_dm_sec_cm	2.260s	1.373us	0	5	0.00
		rv_dm_tl_intg_err	2.360s	3.181us	0	20	0.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	2.360s	3.181us	0	20	0.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.100s	1.747us	0	2	0.00
		rv_dm_debug_disabled	2.060s	1.277us	0	2	0.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	2.100s	1.747us	0	2	0.00
		rv_dm_debug_disabled	2.060s	1.277us	0	2	0.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	2.350s	2.819us	0	2	0.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.380s	1.037us	0	10	0.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	2.240s	828.356ns	0	4	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	2.240s	828.356ns	0	4	0.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.380s	1.037us	0	10	0.00
V2S		TOTAL			0	41	0.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.330s	1.582us	0	10	0.00
V3		TOTAL			0	10	0.00
	Unmapped tests	rv_dm_scanmode	1.850s	1.145us	0	1	0.00
		TOTAL			0	483	0.00

Failure Buckets

• Offending '(!$isunknown(lc_en_o))' has 483 failures:

  • Test rv_dm_csr_aliasing has 5 failures.

    • 0.rv_dm_csr_aliasing.53166133361637347667880277807222962718905146285728016441539607885160466200635
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   1249022 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   1249022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_csr_aliasing.104743942705479060696762268487783643852122803719748418179004233228526854032499
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @    720348 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @    720348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test rv_dm_smoke has 2 failures.

    • 0.rv_dm_smoke.50151711668381248897221748566343516088918850528822511369366288236451475984468
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2818622 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2818622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_smoke.80418292366997306129811992854010203060265730643289569275286131066554959108463
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2980447 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2980447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.6313558365478125395113113573379928671189900499527615595583838920593415562433
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @    765418 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @    765418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.

    • 0.rv_dm_jtag_dtm_csr_hw_reset.97315800284625525464878483142152313900695607554347094828889653320932371598006
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2591234 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2591234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_jtag_dtm_csr_hw_reset.8743788423363644043068202764726909052073231608614774515980203800778510587631
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @    601018 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @    601018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test rv_dm_jtag_dtm_csr_rw has 20 failures.

    • 0.rv_dm_jtag_dtm_csr_rw.2958645365902238559742860562989437694619404314019933445157124109284530404661
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @    755858 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @    755858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_dm_jtag_dtm_csr_rw.40665185637713248254459607713495886527438790495234892025829204400136079863013
      Line 73, in log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   3749291 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   3749291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 18 more failures.

  • ... and 48 more tests.

• Job killed most likely because its dependent job failed. has 2 failures:
  • Test rv_dm has 2 failures.

    • cov_merge
      Log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/cov_merge/merged.vdb/cov_merge.log

    • cov_report
      Log /nightly/runs/scratch/dj-sw-nightly/rv_dm-sim-vcs/cov_report/cov_report.log