RV_TIMER Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	29.358m	459.439ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.270s	18.295us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.250s	42.906us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.490s	363.474us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.290s	70.618us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	3.010s	32.070us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.250s	42.906us	20	20	100.00
		rv_timer_csr_aliasing	2.290s	70.618us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	20.581m	138.229ms	48	50	96.00
V2	disabled	rv_timer_disabled	6.257m	850.764ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	30.253m	1.157s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	30.253m	1.157s	50	50	100.00
V2	stress	rv_timer_stress_all	1.073h	2.771s	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.290s	41.719us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.780s	582.236us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.780s	582.236us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.270s	18.295us	5	5	100.00
		rv_timer_csr_rw	2.250s	42.906us	20	20	100.00
		rv_timer_csr_aliasing	2.290s	70.618us	5	5	100.00
		rv_timer_same_csr_outstanding	2.570s	42.777us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.270s	18.295us	5	5	100.00
		rv_timer_csr_rw	2.250s	42.906us	20	20	100.00
		rv_timer_csr_aliasing	2.290s	70.618us	5	5	100.00
		rv_timer_same_csr_outstanding	2.570s	42.777us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	2.520s	34.232us	5	5	100.00
		rv_timer_tl_intg_err	3.100s	429.643us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.100s	429.643us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.418m	7.740ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			580	620	93.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.84	100.00	99.36	100.00	--	100.00	100.00	99.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test rv_timer_stress_all_with_rand_reset has 36 failures.
  - 0.rv_timer_stress_all_with_rand_reset.72839149373542420294212449753671593045750407525529354096592178610755312614491
    Line 74, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 796585435 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 796585435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_stress_all_with_rand_reset.42992932305042223398753853089798467378475682169545923163440747855351355703295
    Line 111, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2405261425 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2405261425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 34 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test rv_timer_random_reset has 2 failures.

4.rv_timer_random_reset.105303572679161014650215641518260431983051446630795800054099204174074621122850
Line 74, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/4.rv_timer_random_reset/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.rv_timer_random_reset.29590460290873284649092612855010817154156681843226124660350137344718573984716
Line 75, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/48.rv_timer_random_reset/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_disabled has 2 failures.

12.rv_timer_disabled.104360989178079039144817955355685475876978759052939528039734822111858158830208
Line 72, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/12.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.rv_timer_disabled.24926866963555004027329298463384240753866756605070850119633567715947188604165
Line 72, in log /nightly/runs/scratch/dj-sw-nightly/rv_timer-sim-vcs/29.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---