SPI_HOST Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.317m	20.411ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	17.232us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	28.734us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	1.307ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	201.230us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	35.014us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	28.734us	20	20	100.00
		spi_host_csr_aliasing	5.000s	201.230us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	24.715us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	90.062us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	42.000s	42.773us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.033m	58.862ms	50	50	100.00
		spi_host_error_cmd	41.000s	46.315us	50	50	100.00
		spi_host_event	7.650m	15.790ms	50	50	100.00
V2	clock_rate	spi_host_speed	46.000s	423.590us	50	50	100.00
V2	speed	spi_host_speed	46.000s	423.590us	50	50	100.00
V2	chip_select_timing	spi_host_speed	46.000s	423.590us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.017m	7.804ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	41.000s	145.500us	50	50	100.00
V2	cpol_cpha	spi_host_speed	46.000s	423.590us	50	50	100.00
V2	full_cycle	spi_host_speed	46.000s	423.590us	50	50	100.00
V2	duplex	spi_host_smoke	6.317m	20.411ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	6.317m	20.411ms	50	50	100.00
V2	stress_all	spi_host_stress_all	4.733m	15.917ms	49	50	98.00
V2	spien	spi_host_spien	1.250m	11.359ms	50	50	100.00
V2	stall	spi_host_status_stall	6.383m	43.989ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	41.000s	37.914us	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.033m	58.862ms	50	50	100.00
V2	alert_test	spi_host_alert_test	41.000s	25.754us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	16.786us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	460.830us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	460.830us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	17.232us	5	5	100.00
		spi_host_csr_rw	5.000s	28.734us	20	20	100.00
		spi_host_csr_aliasing	5.000s	201.230us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	25.903us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	17.232us	5	5	100.00
		spi_host_csr_rw	5.000s	28.734us	20	20	100.00
		spi_host_csr_aliasing	5.000s	201.230us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	25.903us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	102.089us	20	20	100.00
		spi_host_sec_cm	41.000s	42.070us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	102.089us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	56.300m	100.002ms	2	10	20.00
		TOTAL			830	840	98.81

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.32	96.76	93.24	98.70	94.80	88.02	100.00	97.21	91.56

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:

  • Test spi_host_upper_range_clkdiv has 5 failures.

    • 0.spi_host_upper_range_clkdiv.17822158363946852151433258047394674626873431850881656316539664321576544231820
      Line 173, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002441934 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x94f59114, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100002441934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.spi_host_upper_range_clkdiv.9173924759158161334996005336323371932784718523264769187061300358225325080665
      Line 157, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002557729 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x659005d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100002557729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 1.spi_host_upper_range_clkdiv.13315569271895412959559885077372747076658231530902612615818045864011160851818
      Line 190, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 176129588864 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x5eb9614, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
        UVM_INFO @ 176129588864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 6.spi_host_upper_range_clkdiv.87448662774291939388307762076835006905850231401348399133524532494486010104713
      Line 185, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 199618057259 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xeffd3354, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
        UVM_INFO @ 199618057259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 9.spi_host_upper_range_clkdiv.22645362078278809999876309294207216956416815085471356693823505610220364865556
      Log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=46) has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 26.spi_host_stress_all.70176683571264951649307424046641833550869450258177692826417043470097649133848
      Line 374, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/26.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 15916860706 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa9cefcd4, Comparison=CompareOpEq, exp_data=0x0, call_count=46)
        UVM_INFO @ 15916860706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=40) has 1 failures:

  • Test spi_host_sw_reset has 1 failures.

    • 45.spi_host_sw_reset.2815099193046850646157504963065480922393028726433576067190431260124292901663
      Line 295, in log /nightly/runs/scratch/dj-sw-nightly/spi_host-sim-xcelium/45.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 10051585060 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xb0255294, Comparison=CompareOpEq, exp_data=0x0, call_count=40)
        UVM_INFO @ 10051585060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---