UART Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: 9464f06a4d

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	41.870s	11.104ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	3.610s	1.077ms	5	5	100.00
V1	csr_rw	uart_csr_rw	3.330s	46.596us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	4.470s	1.373ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	3.500s	82.073us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	3.590s	107.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	3.330s	46.596us	20	20	100.00
		uart_csr_aliasing	3.500s	82.073us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.056m	97.191ms	50	50	100.00
V2	parity	uart_smoke	41.870s	11.104ms	50	50	100.00
		uart_tx_rx	3.056m	97.191ms	50	50	100.00
V2	parity_error	uart_intr	12.651m	599.793ms	50	50	100.00
		uart_rx_parity_err	3.842m	131.232ms	50	50	100.00
V2	watermark	uart_tx_rx	3.056m	97.191ms	50	50	100.00
		uart_intr	12.651m	599.793ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.457m	212.778ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	5.408m	89.943ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.071m	264.712ms	299	300	99.67
V2	rx_frame_err	uart_intr	12.651m	599.793ms	50	50	100.00
V2	rx_break_err	uart_intr	12.651m	599.793ms	50	50	100.00
V2	rx_timeout	uart_intr	12.651m	599.793ms	50	50	100.00
V2	perf	uart_perf	24.939m	35.324ms	50	50	100.00
V2	sys_loopback	uart_loopback	36.350s	13.084ms	50	50	100.00
V2	line_loopback	uart_loopback	36.350s	13.084ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.089m	203.417ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.853m	45.489ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	29.520s	6.318ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	52.790s	7.696ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.986m	167.094ms	50	50	100.00
V2	stress_all	uart_stress_all	23.079m	211.878ms	50	50	100.00
V2	alert_test	uart_alert_test	2.180s	18.485us	50	50	100.00
V2	intr_test	uart_intr_test	3.430s	138.116us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	4.380s	218.315us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	4.380s	218.315us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	3.610s	1.077ms	5	5	100.00
		uart_csr_rw	3.330s	46.596us	20	20	100.00
		uart_csr_aliasing	3.500s	82.073us	5	5	100.00
		uart_same_csr_outstanding	3.410s	25.697us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	3.610s	1.077ms	5	5	100.00
		uart_csr_rw	3.330s	46.596us	20	20	100.00
		uart_csr_aliasing	3.500s	82.073us	5	5	100.00
		uart_same_csr_outstanding	3.410s	25.697us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	2.700s	1.014ms	5	5	100.00
		uart_tl_intg_err	3.770s	268.034us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.770s	268.034us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.760m	5.833ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.18	98.25	91.55	--	98.14	100.00	99.50

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

  • Test uart_fifo_full has 1 failures.

    • 0.uart_fifo_full.93766832625315170398351600956054122748189159434739096028935138197541945405609
      Line 69, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/0.uart_fifo_full/latest/run.log

        UVM_ERROR @   1892876 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 5286912481 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 1/6
        UVM_INFO @ 6954969125 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 2/6
        UVM_INFO @ 7539480606 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 3/6
        UVM_INFO @ 14301372414 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 4/6
      

  • Test uart_fifo_reset has 1 failures.

    • 94.uart_fifo_reset.74441645560687491856841882422289510800185574702320365451033906557513489624936
      Line 69, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/94.uart_fifo_reset/latest/run.log

        UVM_ERROR @   3046616 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 19811709574 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
        UVM_INFO @ 115178982344 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
        UVM_INFO @ 148286003200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
        UVM_INFO @ 148394038050 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6
      

• UVM_ERROR (cip_base_vseq.sv:890) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 92.uart_stress_all_with_rand_reset.33200012208091112022124924511722790498753614089607460716218094908173184247683
      Line 89, in log /nightly/runs/scratch/dj-sw-nightly/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1123014742 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1123040009 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1123040009 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 3/5
        UVM_INFO @ 1123058220 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1