CHIP Simulation Results

Friday March 14 2025 17:31:47 UTC

GitHub Revision: `9464f06a4d`

Branch: dj-sw-nightly

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.455m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.455m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	39.882s		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.337m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.355m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	1.085m		0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	1.085m		0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	1.085m		0	3	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.540m		0	3	0.00
		chip_sw_example_manufacturer	37.692s		0	3	0.00
		chip_sw_example_concurrency	37.691s		0	3	0.00
		chip_sw_uart_smoketest_signed	15.871s		0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset	16.027s		0	5	0.00
V1	csr_rw	chip_csr_rw	3.196m	5.353ms	0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.874m	8.953ms	1	5	20.00
V1	csr_aliasing	chip_csr_aliasing	1.156s		0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	29.211s		0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.156s		0	5	0.00
		chip_csr_rw	3.196m	5.353ms	0	20	0.00
V1	xbar_smoke	xbar_smoke	33.352s		4	100	4.00
V1		TOTAL			5	205	2.44
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	30.529s		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	1.150m		0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	1.084m		0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.150m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	13.250s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.286m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	26.018s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	15.076s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	15.076s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	35.620s		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	33.591s		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.575m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.575m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.615m	4.696ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.427m	3.677ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	16.128s		0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	27.378s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	26.390s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.254s		0	3	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.177s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	1.008s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	1.008s		0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	1.012s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	25.039s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	25.039s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	40.230s		0	5	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	1.116s		0	3	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.204s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	1.108s		0	3	0.00
		chip_sw_aes_idle	15.263s		0	3	0.00
		chip_sw_hmac_enc_idle	1.008s		0	3	0.00
		chip_sw_kmac_idle	28.364s		0	3	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	1.204s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	1.210s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	40.176s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	15.031s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	40.179s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.019s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.136s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	1.008s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	40.179s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.019s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.136s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	1.008s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	26.422s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.141s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	25.134s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.008s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.008s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.457s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	38.804s		0	3	0.00
		chip_sw_clkmgr_jitter	26.845s		0	3	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.032s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.140s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	15.172s		0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.135s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	32.927s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	25.767s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.012s		0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.405s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	15.031s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	1.008s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	1.012s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	1.540m		0	100	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	25.433s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	25.039s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	40.232s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	25.433s		0	3	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	1.051s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.714s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	24.708s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	1.180s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	15.460s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	1.540m		0	100	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	16.128s		0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	1.039s		0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	29.503s		0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	25.455s		0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	25.290s		0	3	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	1.540m		0	100	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.083s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	50.975s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	1.540m		0	100	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	1.116s		0	3	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	40.345s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	25.455s		0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.937s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.371m		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	41.283s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	1.012s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.074s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	15.904s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	50.975s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.016m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	1.008s		0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.016m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	54.673s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	56.776s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	58.908s		0	3	0.00
		chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	1.008s		0	3	0.00
		chip_sw_rom_ctrl_integrity_check	40.175s		0	3	0.00
		chip_sw_sram_ctrl_execution_main	1.012s		0	3	0.00
		chip_prim_tl_access	20.614s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	40.179s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.019s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.136s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	1.008s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	1.008s		0	3	0.00
		chip_rv_dm_lc_disabled	1.254s		0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	13.470s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.141s		0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	28.275s		0	3	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	15.263s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.008s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.008s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.008s		0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.012s		0	3	0.00
		chip_sw_kmac_mode_kmac	15.086s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.457s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	1.008s		0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	46.822s		0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	1.014m		0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	28.364s		0	3	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.203s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.203s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.011s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.008s		0	3	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.008s		0	3	0.00
		chip_sw_edn_entropy_reqs	1.135s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	1.008s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.008s		0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	16.052s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	26.422s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	1.108s		0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	1.108s		0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	1.108s		0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	40.650s		0	3	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	40.175s		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	40.175s		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	16.019s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	38.804s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	1.012s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	1.540m		0	100	0.00
		chip_sw_data_integrity_escalation	1.575m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	40.650s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation	1.008s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	16.019s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	15.870s		0	3	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	40.650s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation	1.008s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	16.019s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	15.870s		0	3	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	25.063s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.016m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.016m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	54.673s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	56.776s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	58.908s		0	3	0.00
		chip_sw_lc_ctrl_transition	55.685s		0	15	0.00
		chip_prim_tl_access	20.614s		0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	20.614s		0	3	0.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	56.759s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	56.759s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	15.031s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	26.422s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.141s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	25.134s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.008s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.008s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.457s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	38.804s		0	3	0.00
		chip_sw_clkmgr_jitter	26.845s		0	3	0.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	29.179s		0	5	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	29.179s		0	5	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	42.853s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.008s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	42.853s		0	3	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	1.112s		0	3	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	1.112s		0	3	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	17.704s		0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	15.045s		0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	12.056s		0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	40.151s		0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	1.008s		0	3	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	31.907s		0	3	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	15.870s		0	3	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	1.039s		0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	1.039s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	1.225s		0	3	0.00
		chip_sw_aon_timer_smoketest	27.150s		0	3	0.00
		chip_sw_clkmgr_smoketest	1.248s		0	3	0.00
		chip_sw_csrng_smoketest	1.265s		0	3	0.00
		chip_sw_gpio_smoketest	25.653s		0	3	0.00
		chip_sw_hmac_smoketest	26.379s		0	3	0.00
		chip_sw_kmac_smoketest	15.833s		0	3	0.00
		chip_sw_otbn_smoketest	46.763s		0	3	0.00
		chip_sw_otp_ctrl_smoketest	40.548s		0	3	0.00
		chip_sw_rv_plic_smoketest	1.153s		0	3	0.00
		chip_sw_rv_timer_smoketest	40.485s		0	3	0.00
		chip_sw_rstmgr_smoketest	1.153s		0	3	0.00
		chip_sw_sram_ctrl_smoketest	33.157s		0	3	0.00
		chip_sw_uart_smoketest	1.013s		0	3	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	16.121s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	15.871s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	30.529s		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.100s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	56.754s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	56.752s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	49.802s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	46.591s		0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	28.450s		0	3	0.00
		chip_rv_dm_lc_disabled	1.254s		0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	46.588s		0	3	0.00
		chip_sw_lc_walkthrough_prod	44.559s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	45.650s		0	3	0.00
		chip_sw_lc_walkthrough_rma	44.324s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	28.450s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	41.698s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	37.589s		0	3	0.00
		rom_volatile_raw_unlock	34.861s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	48.595s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.388m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	28.500s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	31.812s		0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	31.812s		0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.156s		0	5	0.00
		chip_same_csr_outstanding	4.607m	6.219ms	0	20	0.00
		chip_csr_hw_reset	16.027s		0	5	0.00
		chip_csr_rw	3.196m	5.353ms	0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing	1.156s		0	5	0.00
		chip_same_csr_outstanding	4.607m	6.219ms	0	20	0.00
		chip_csr_hw_reset	16.027s		0	5	0.00
		chip_csr_rw	3.196m	5.353ms	0	20	0.00
V2	xbar_base_random_sequence	xbar_random	1.994m	400.271us	3	100	3.00
V2	xbar_random_delay	xbar_smoke_zero_delays	33.348s		2	100	2.00
		xbar_smoke_large_delays	4.534m	2.678ms	6	100	6.00
		xbar_smoke_slow_rsp	5.758m	2.451ms	8	100	8.00
		xbar_random_zero_delays	1.032m	67.703us	9	100	9.00
		xbar_random_large_delays	18.632m	11.112ms	5	100	5.00
		xbar_random_slow_rsp	31.226m	13.216ms	3	100	3.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.257m	198.685us	4	100	4.00
		xbar_error_and_unmapped_addr	54.740s	172.543us	10	100	10.00
V2	xbar_error_cases	xbar_error_random	31.163s		1	100	1.00
		xbar_error_and_unmapped_addr	54.740s	172.543us	10	100	10.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.498m	468.063us	5	100	5.00
		xbar_access_same_device_slow_rsp	48.239m	20.520ms	7	100	7.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.304m	291.230us	8	100	8.00
V2	xbar_stress_all	xbar_stress_all	15.805m	3.034ms	4	100	4.00
		xbar_stress_all_with_error	12.986m	2.910ms	5	100	5.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	30.288m	5.462ms	6	100	6.00
		xbar_stress_all_with_reset_error	18.361m	2.748ms	5	100	5.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.140s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.898s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.139s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.068s		0	3	0.00
		rom_e2e_asm_init_dev	54.395s		0	3	0.00
		rom_e2e_asm_init_prod	1.008s		0	3	0.00
		rom_e2e_asm_init_prod_end	1.144s		0	3	0.00
		rom_e2e_asm_init_rma	1.155s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.011s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	26.347s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.011s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	26.356s		0	3	0.00
V2		TOTAL			91	2466	3.69
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	27.698s		0	3	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.031s		0	3	0.00
V2S		TOTAL			0	6	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	1.039s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	1.540m		0	100	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	57.829s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	58.901s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1.135s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0			0	1	0.00
		rom_e2e_jtag_inject_dev			0	1	0.00
		rom_e2e_jtag_inject_rma			0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	47.067s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	1.540m		0	3	0.00
		chip_sw_dma_inline_hashing	1.141s		0	3	0.00
		chip_sw_dma_abort	1.138s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	43.916s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	43.589s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	25.468s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	15.780s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	26.331s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	15.745s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	1.116s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	15.055s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	1.163s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	16.078s		0	3	0.00
		chip_sw_mbx_smoketest	15.831s		0	3	0.00
		TOTAL			96	2739	3.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
52.13	61.33	49.25	35.86	--	49.85	38.13	78.36

Failure Buckets

Job returned non-zero exit code has 2040 failures:

Test chip_csr_aliasing has 5 failures.

0.chip_csr_aliasing.105037003002285125717132678535958474688771697627861924123651475029693540636021
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 105037003002285125717132678535958474688771697627861924123651475029693540636021' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest run_opts='+test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=325883253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_aliasing.325883253' seed=105037003002285125717132678535958474688771697627861924123651475029693540636021 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

1.chip_csr_aliasing.96461598177758576098248178573451802420453996325071263876143411839120456791542
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 96461598177758576098248178573451802420453996325071263876143411839120456791542' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest run_opts='+test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3402348022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_aliasing.3402348022' seed=96461598177758576098248178573451802420453996325071263876143411839120456791542 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 3 more failures.

Test chip_same_csr_outstanding has 15 failures.

0.chip_same_csr_outstanding.58158426046528520322700721333275788942133302737289719620138689872952251070752
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 58158426046528520322700721333275788942133302737289719620138689872952251070752
  /bin/bash: fork: retry: Resource temporarily unavailable
  /bin/bash: fork: retry: Resource temporarily unavailable
  /bin/bash: fork: retry: Resource temporarily unavailable
  /bin/bash: fork: retry: Resource temporarily unavailable
  /bin/bash: fork: Resource temporarily unavailable
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 254

1.chip_same_csr_outstanding.55943401451624289595038414405050048959534923541714709581976512890935872832166
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 55943401451624289595038414405050048959534923541714709581976512890935872832166' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/cover_reg_top/simv run_dir=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest run_opts='+test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1553449638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1553449638' seed=55943401451624289595038414405050048959534923541714709581976512890935872832166 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='' uvm_test=chip_base_test uvm_test_seq=chip_common_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 13 more failures.

Test chip_sw_example_rom has 2 failures.

0.chip_sw_example_rom.9720748306580545884836324992059462813700006416634499430782739169854457616116
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Analyzing: target //sw/device/tests:example_test_from_rom_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (701cd0)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 68.172s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

2.chip_sw_example_rom.86898967764882045467928288454286498134554916737373107779207683309720211950247
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 86898967764882045467928288454286498134554916737373107779207683309720211950247' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1451887271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1451887271' seed=86898967764882045467928288454286498134554916737373107779207683309720211950247 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images=//sw/device/tests:example_test_from_rom:0:test_in_rom uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

Test chip_sw_example_manufacturer has 2 failures.

0.chip_sw_example_manufacturer.73680282525963045968144257220320147353666439222015183439798893901180224367372
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (2b0454)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.165s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

2.chip_sw_example_manufacturer.66402264072726683881327670591683003843385087729532248679391295815479402010926
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 66402264072726683881327670591683003843385087729532248679391295815479402010926' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4109211950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.4109211950' seed=66402264072726683881327670591683003843385087729532248679391295815479402010926 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

Test chip_sw_example_concurrency has 2 failures.

0.chip_sw_example_concurrency.735980174364786985529718497085833975841608481049394289492247485040364631588
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

  Target //sw/device/tests:example_concurrency_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted: Target //sw/device/tests:example_concurrency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_concurrency_test_sim_dv (a8b93f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.526s, Critical Path: 0.22s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

2.chip_sw_example_concurrency.59242758481315701240763721694914943041443164544361341885023491580782012056432
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 59242758481315701240763721694914943041443164544361341885023491580782012056432' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest run_opts='+sw_build_device=sim_dv +sw_images=example_concurrency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=676905840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.676905840' seed=59242758481315701240763721694914943041443164544361341885023491580782012056432 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 206 more tests.

Error: failed to create UCLI thread: Resource temporarily unavailable. has 357 failures:
- Test chip_csr_bit_bash has 4 failures.
  - 0.chip_csr_bit_bash.72959003388380189711894668886372388616569588271809250610166067644314525892393
    Line 128, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - 1.chip_csr_bit_bash.73403232161916722079344800548875724330839434434192527076124114507396397957163
    Line 125, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - ... and 2 more failures.
- Test chip_prim_tl_access has 1 failures.
  - 0.chip_prim_tl_access.77597925844732347552408685864054967639979799791709234812919853500566023807826
    Line 127, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
- Test xbar_smoke has 20 failures.
  - 0.xbar_smoke.103535973054713821999186619594523646842497010947343825860791484839231845176664
    Line 124, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.xbar_smoke/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - 4.xbar_smoke.114054808227725029397782977304866867550793611296477523048123355929305944510087
    Line 125, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/4.xbar_smoke/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - ... and 18 more failures.
- Test xbar_smoke_zero_delays has 21 failures.
  - 0.xbar_smoke_zero_delays.103298462982972187143570911078875677681208853259103207163704783735715500800543
    Line 124, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - 9.xbar_smoke_zero_delays.4807636068471951642614745727967214051769031465841908679836828928315334233438
    Line 124, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/9.xbar_smoke_zero_delays/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - ... and 19 more failures.
- Test xbar_access_same_device has 22 failures.
  - 0.xbar_access_same_device.65685941163797577575222175341137951472996221920356819845764447037869702323004
    Line 124, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - 8.xbar_access_same_device.95138807345743904261207747268797091928907170330946351486517695659312458777887
    Line 125, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device/latest/run.log
```
  Error: failed to create UCLI thread: Resource temporarily unavailable.
  [make]: post_run
  [make]: run_result
```
  - ... and 20 more failures.
- ... and 22 more tests.
Job timed out after * minutes has 228 failures:
- Test chip_sw_rstmgr_cpu_info has 2 failures.
  - 0.chip_sw_rstmgr_cpu_info.101080907842617269712150038109873147046299732286168770323131036661261354866658
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_rstmgr_cpu_info.54988715766133625332938709610562499136419603364203540532381829408697910736591
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_pwrmgr_full_aon_reset has 2 failures.
  - 0.chip_sw_pwrmgr_full_aon_reset.67482325058503992186047706334108905917788267080055321795533068331131520021180
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_pwrmgr_full_aon_reset.56936216468064916761462462447101908739121566719141099442058692660925097943719
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_pwrmgr_main_power_glitch_reset has 2 failures.
  - 0.chip_sw_pwrmgr_main_power_glitch_reset.93315286978340433340500822535198872037025006946930729120631510725406827889722
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_pwrmgr_main_power_glitch_reset.91459459697600158399805668471366043259874594626522452221036757493688358720833
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_main_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_pwrmgr_sleep_power_glitch_reset has 2 failures.
  - 0.chip_sw_pwrmgr_sleep_power_glitch_reset.42782508661254362458742520935772175796740199546335863123902612103493130903104
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_pwrmgr_sleep_power_glitch_reset.86433303550675207059930150563172902811401603434673263840505162907504230412287
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_pwrmgr_deep_sleep_power_glitch_reset has 2 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.6185356984473628948820034890934331211541207531118859083214739332438247754728
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.47107556475176579674553539501228056054537092849027901882199645695222218511238
    Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 213 more tests.
Error: Failed to generate features has 12 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.76165839651065594361304183491795999168638341583958308159167971239819000674487
    Line 339, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  Error: Failed to generate features

  Caused by:
      0: Failed to copy project with proc macro deps made direct
      1: Failed to run cargo metadata to list transitive proc macros
```
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.106110865267433407224529638005606394657257699546694791268063692449520031573868
    Line 248, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  Error: Failed to generate features

  Caused by:
      0: Failed to copy project with proc macro deps made direct
      1: Failed to run cargo metadata to list transitive proc macros
```
- Test chip_sw_spi_device_pass_through has 1 failures.
  - 0.chip_sw_spi_device_pass_through.89589714573816431958398554081359835306501233831102887519346440207472418943067
    Line 240, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
```
  Error: Failed to generate features

  Caused by:
      0: Failed to copy project with proc macro deps made direct
      1: Failed to run cargo metadata to list transitive proc macros
```
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.49961868446843839757554963603498749872648068007114024435833735504189625950710
    Line 244, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  Error: Failed to generate features

  Caused by:
      0: Failed to copy project with proc macro deps made direct
      1: Failed to run cargo metadata to list transitive proc macros
```
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.43953820723522258739537787081250087007633896818914916740969939045636663731472
    Line 245, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  Error: Failed to generate features

  Caused by:
      0: Failed to copy project with proc macro deps made direct
      1: Failed to run cargo metadata to list transitive proc macros
```
- ... and 7 more tests.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44414) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.91558401478712982521494394392409520837999636217711931567890393183278704135237
Line 5661, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4696.111694 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44414) { a_addr: 'h30480000  a_data: 'hf3b8cb3e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h1  a_user: 'h248ff  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4696.111694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.31767902671317934957292101935867606831870221561134235185560396127093923613055
Line 5661, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3677.337574 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44414) { a_addr: 'h30480000  a_data: 'h92f48d19  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h1  a_user: 'h248bf  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3677.337574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:293) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:
- Test chip_same_csr_outstanding has 2 failures.
  - 8.chip_same_csr_outstanding.106705865670030387051219343532297214020770227202269245805826936497041603902462
    Line 258, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/8.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 6218.609846 us: (cip_base_vseq.sv:293) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (150 [0x96] vs 153 [0x99]) addr 0x30170014 read out mismatch
  UVM_INFO @ 6218.609846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.chip_same_csr_outstanding.81014157279321500542114809981342249394238648568057479239891284756303017513143
    Line 257, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/9.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 3431.471400 us: (cip_base_vseq.sv:293) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (150 [0x96] vs 153 [0x99]) addr 0x30170014 read out mismatch
  UVM_INFO @ 3431.471400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[COFW] Cannot open file has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.13224047520661711960407641903543202245410157227472059213457354730926107255394
    Line 277, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[COFW] Cannot open file
    File
    '/nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/pad_ctrl_test_mode/simv.cst/testcases/extracted_r_140_p_7_inconsistent_constraints.sv'
    cannot be opened for writing.
    Please make sure permissions/space exists.
```
UVM_ERROR @ * us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_boot_status.cpu_fetch_en reset value: * has 1 failures:
- Test chip_csr_rw has 1 failures.
  - 17.chip_csr_rw.30468728504003764134907848569204643766626364482804422509369424766062054568602
    Line 260, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/17.chip_csr_rw/latest/run.log
```
  UVM_ERROR @ 5353.127128 us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_boot_status.cpu_fetch_en reset value: 0x0
  UVM_INFO @ 5353.127128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```