AES/MASKED Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	65.163us	1	1	100.00
V1	smoke	aes_smoke	10.000s	445.622us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	70.327us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	73.382us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	586.883us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	366.962us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	91.835us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	73.382us	20	20	100.00
		aes_csr_aliasing	6.000s	366.962us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	445.622us	50	50	100.00
		aes_config_error	25.000s	1.296ms	50	50	100.00
		aes_stress	1.500m	5.126ms	50	50	100.00
V2	key_length	aes_smoke	10.000s	445.622us	50	50	100.00
		aes_config_error	25.000s	1.296ms	50	50	100.00
		aes_stress	1.500m	5.126ms	50	50	100.00
V2	back2back	aes_stress	1.500m	5.126ms	50	50	100.00
		aes_b2b	24.000s	455.961us	50	50	100.00
V2	backpressure	aes_stress	1.500m	5.126ms	50	50	100.00
V2	multi_message	aes_smoke	10.000s	445.622us	50	50	100.00
		aes_config_error	25.000s	1.296ms	50	50	100.00
		aes_stress	1.500m	5.126ms	50	50	100.00
		aes_alert_reset	32.000s	3.502ms	48	50	96.00
V2	failure_test	aes_man_cfg_err	6.000s	66.983us	50	50	100.00
		aes_config_error	25.000s	1.296ms	50	50	100.00
		aes_alert_reset	32.000s	3.502ms	48	50	96.00
V2	trigger_clear_test	aes_clear	17.000s	595.674us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	29.000s	9.310ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	32.000s	3.502ms	48	50	96.00
V2	stress	aes_stress	1.500m	5.126ms	50	50	100.00
V2	sideload	aes_stress	1.500m	5.126ms	50	50	100.00
		aes_sideload	25.000s	1.076ms	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	469.072us	50	50	100.00
V2	stress_all	aes_stress_all	49.000s	1.578ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	56.389us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	113.424us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	113.424us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	70.327us	5	5	100.00
		aes_csr_rw	5.000s	73.382us	20	20	100.00
		aes_csr_aliasing	6.000s	366.962us	5	5	100.00
		aes_same_csr_outstanding	6.000s	158.504us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	70.327us	5	5	100.00
		aes_csr_rw	5.000s	73.382us	20	20	100.00
		aes_csr_aliasing	6.000s	366.962us	5	5	100.00
		aes_same_csr_outstanding	6.000s	158.504us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	18.000s	1.742ms	50	50	100.00
V2S	fault_inject	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	208.917us	12	20	60.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	208.917us	12	20	60.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	208.917us	12	20	60.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	208.917us	12	20	60.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	127.162us	13	20	65.00
V2S	tl_intg_err	aes_sec_cm	1.183m	17.008ms	4	5	80.00
		aes_tl_intg_err	7.000s	596.529us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	596.529us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	32.000s	3.502ms	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	208.917us	12	20	60.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	445.622us	50	50	100.00
		aes_stress	1.500m	5.126ms	50	50	100.00
		aes_alert_reset	32.000s	3.502ms	48	50	96.00
		aes_core_fi	35.000s	10.006ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	208.917us	12	20	60.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	106.779us	50	50	100.00
		aes_stress	1.500m	5.126ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.500m	5.126ms	50	50	100.00
		aes_sideload	25.000s	1.076ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	106.779us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	106.779us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	106.779us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	106.779us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	106.779us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.500m	5.126ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.500m	5.126ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	40.000s	2.211ms	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
		aes_ctr_fi	6.000s	54.949us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	40.000s	2.211ms	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.027ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	40.000s	2.211ms	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_ctr_fi	6.000s	54.949us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
		aes_ctr_fi	6.000s	54.949us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	32.000s	3.502ms	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
		aes_ctr_fi	6.000s	54.949us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
		aes_ctr_fi	6.000s	54.949us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_ctr_fi	6.000s	54.949us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	40.000s	2.211ms	47	50	94.00
		aes_control_fi	51.000s	10.008ms	270	300	90.00
		aes_cipher_fi	59.000s	10.027ms	344	350	98.29
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	36.000s	4.736ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1532	1602	95.63

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.59	96.43	99.43	95.70	97.99	97.78	98.96	98.59

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 21 failures:

Test aes_shadow_reg_errors has 8 failures.

1.aes_shadow_reg_errors.49563847982244508593278899300692903133460187012048699962199446335952051434132
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @   7305177 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   7305177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_shadow_reg_errors.84603807211843721430270812931437913813039605411279342772982803996500848371942
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @   5609359 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   5609359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aes_fi has 3 failures.

4.aes_fi.68277888139020509672203821544937455809506069910696281871127209640898416220137
Line 2651, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_fi/latest/run.log

  UVM_FATAL @  32511807 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  32511807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.aes_fi.79628629365283118372969417043847873662192484130584449732069504746132038596396
Line 4694, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/21.aes_fi/latest/run.log

  UVM_FATAL @  13084419 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  13084419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aes_shadow_reg_errors_with_csr_rw has 7 failures.

10.aes_shadow_reg_errors_with_csr_rw.84090130701913899027026767347937300232516084036743994574149170254722938257146
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/10.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  19792266 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  19792266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.aes_shadow_reg_errors_with_csr_rw.48161075272778637560872172855505169367147007421441919478358251590885722749806
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/12.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 127103269 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 127103269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aes_alert_reset has 2 failures.

18.aes_alert_reset.30171242745245269528584185365291973238063919538915468099874953719862735191842
Line 2894, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/18.aes_alert_reset/latest/run.log

  UVM_FATAL @  20318796 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  20318796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aes_alert_reset.84505778700314580821953843586045083325159132072219017263777856095398017331866
Line 690, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/22.aes_alert_reset/latest/run.log

  UVM_FATAL @  24637057 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  24637057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_core_fi has 1 failures.

28.aes_core_fi.94246205175212911259587252485648096698182744415872520492282809776779754872222
Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/28.aes_core_fi/latest/run.log

  UVM_FATAL @  15363250 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  15363250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job timed out after * minutes has 20 failures:
- Test aes_control_fi has 20 failures.
  - 5.aes_control_fi.107660440267501604093748348673667234189758245704136628338701870256242263587553
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 11.aes_control_fi.74500734416657343342720886647563019008090711242858965663516250529896137341141
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 18 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 17.aes_control_fi.43398474419256676914336540672765721463423742022075815114504311629117265878471
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10172030332 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10172030332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.aes_control_fi.72899137624746656463826428990015384443105910577077929850416567123856227648468
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10057591184 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10057591184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.42309969503914675598691461270833600372572000153743197625191754392040466327191
Line 439, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 341788915 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 341788915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.66080727516014900074036349458269612942654511180207269304822083309592715291611
Line 453, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 703390217 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 703390217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 72.aes_cipher_fi.59988760608708546441457120026930964648232811091738120699720619728167091145840
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013235939 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013235939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 132.aes_cipher_fi.36603691243085350080964866055024221304580498395861880174161192388959007836612
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/132.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018270780 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018270780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

7.aes_core_fi.96373903516023167259282766102839414457226605884397071521599080579799871079245
Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_core_fi/latest/run.log

  UVM_FATAL @ 10021111148 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021111148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

43.aes_core_fi.42969600389601801630918410406085272633236036922119311768931939568888386620649
Line 139, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/43.aes_core_fi/latest/run.log

  UVM_FATAL @ 10006422309 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006422309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.115289900864682331023393982118351153544506292333872971343838437963902473488481
    Line 718, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2835599326 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2835599326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:666) [aes_common_vseq] timeout wait for alert handshake:fatal_fault has 1 failures:
- Test aes_sec_cm has 1 failures.
  - 2.aes_sec_cm.60565054879249852103702277951054957529962057993220473529845623146257690094312
    Line 169, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_sec_cm/latest/run.log
```
  UVM_FATAL @ 10341529368 ps: (cip_base_vseq.sv:666) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 10341529368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.43866412176163597579634017464097851639623430205191619093064545367128676917901
    Line 495, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1010205577 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1010205577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.51373731169831520503799522948882272854035012056404107678724182040498400481803
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 25146629 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 25126629 PS)
  UVM_ERROR @  25146629 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  25146629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```