AES/UNMASKED Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	9.000s	64.578us	1	1	100.00
V1	smoke	aes_smoke	8.000s	92.538us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	103.456us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	93.936us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.857ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	885.145us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	129.927us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	93.936us	20	20	100.00
		aes_csr_aliasing	7.000s	885.145us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	92.538us	50	50	100.00
		aes_config_error	8.000s	96.867us	50	50	100.00
		aes_stress	8.000s	159.980us	50	50	100.00
V2	key_length	aes_smoke	8.000s	92.538us	50	50	100.00
		aes_config_error	8.000s	96.867us	50	50	100.00
		aes_stress	8.000s	159.980us	50	50	100.00
V2	back2back	aes_stress	8.000s	159.980us	50	50	100.00
		aes_b2b	12.000s	421.653us	50	50	100.00
V2	backpressure	aes_stress	8.000s	159.980us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	92.538us	50	50	100.00
		aes_config_error	8.000s	96.867us	50	50	100.00
		aes_stress	8.000s	159.980us	50	50	100.00
		aes_alert_reset	8.000s	128.479us	49	50	98.00
V2	failure_test	aes_man_cfg_err	7.000s	77.379us	50	50	100.00
		aes_config_error	8.000s	96.867us	50	50	100.00
		aes_alert_reset	8.000s	128.479us	49	50	98.00
V2	trigger_clear_test	aes_clear	9.000s	73.682us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	594.779us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	128.479us	49	50	98.00
V2	stress	aes_stress	8.000s	159.980us	50	50	100.00
V2	sideload	aes_stress	8.000s	159.980us	50	50	100.00
		aes_sideload	9.000s	529.894us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	58.302us	50	50	100.00
V2	stress_all	aes_stress_all	23.000s	2.008ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	70.896us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	219.197us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	219.197us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	103.456us	5	5	100.00
		aes_csr_rw	5.000s	93.936us	20	20	100.00
		aes_csr_aliasing	7.000s	885.145us	5	5	100.00
		aes_same_csr_outstanding	6.000s	333.636us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	103.456us	5	5	100.00
		aes_csr_rw	5.000s	93.936us	20	20	100.00
		aes_csr_aliasing	7.000s	885.145us	5	5	100.00
		aes_same_csr_outstanding	6.000s	333.636us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	8.000s	338.528us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	91.894us	11	20	55.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	91.894us	11	20	55.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	91.894us	11	20	55.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	91.894us	11	20	55.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	152.185us	9	20	45.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.636ms	5	5	100.00
		aes_tl_intg_err	7.000s	3.026ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	3.026ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	128.479us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	91.894us	11	20	55.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	92.538us	50	50	100.00
		aes_stress	8.000s	159.980us	50	50	100.00
		aes_alert_reset	8.000s	128.479us	49	50	98.00
		aes_core_fi	32.000s	10.004ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	91.894us	11	20	55.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	77.084us	50	50	100.00
		aes_stress	8.000s	159.980us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	159.980us	50	50	100.00
		aes_sideload	9.000s	529.894us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	77.084us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	77.084us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	77.084us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	77.084us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	77.084us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	159.980us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	159.980us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	122.942us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
		aes_ctr_fi	7.000s	47.693us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	122.942us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	36.000s	10.003ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	122.942us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_ctr_fi	7.000s	47.693us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
		aes_ctr_fi	7.000s	47.693us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	128.479us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
		aes_ctr_fi	7.000s	47.693us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
		aes_ctr_fi	7.000s	47.693us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_ctr_fi	7.000s	47.693us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	122.942us	48	50	96.00
		aes_control_fi	35.000s	10.002ms	285	300	95.00
		aes_cipher_fi	36.000s	10.003ms	325	350	92.86
V2S		TOTAL			920	985	93.40
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	1.692ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1526	1602	95.26

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.25	97.60	94.59	98.76	93.45	97.99	93.33	98.85	97.59

Failure Buckets

Job timed out after * minutes has 23 failures:
- Test aes_control_fi has 9 failures.
  - 10.aes_control_fi.75205672145968037229450833697111403825612735423812137441712190516876805741163
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 12.aes_control_fi.113916440634027120779885903666243729601998048223995686884427511281363120064350
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 14 failures.
  - 26.aes_cipher_fi.40142043093751198426012053228522123352950155908568574145268541678502078387173
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 35.aes_cipher_fi.52767993189736591680429701671878744213518144482345916821670261219056704686867
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 18 failures:

Test aes_shadow_reg_errors has 8 failures.

3.aes_shadow_reg_errors.11955454750655165784295041234287933169271014616534836871920332876160976383916
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  13242593 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  13242593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_shadow_reg_errors.34129543154271534140639804159857489097747669011421121813486685114443788370843
Line 104, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  76138894 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  76138894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aes_shadow_reg_errors_with_csr_rw has 6 failures.

4.aes_shadow_reg_errors_with_csr_rw.64533590767047960735625972530196271900314112680699521857245055104030250538195
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  27901265 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  27901265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_shadow_reg_errors_with_csr_rw.89871617866780494994940465036679432872549658347947157755795172927635052184445
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  43380925 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  43380925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aes_stress_all_with_rand_reset has 2 failures.

6.aes_stress_all_with_rand_reset.70706533717121822774255883361473484724809756797804771320630302677966694759674
Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  17122331 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  17122331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.3749697651295190734511435013809141019293413396977100689133796237224750567948
Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  62186160 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  62186160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 1 failures.

12.aes_alert_reset.30306887086873871226511476601604637883013068713240649010711107623664167371946
Line 868, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_alert_reset/latest/run.log

  UVM_FATAL @  47426179 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  47426179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

15.aes_fi.29422609946983033305023035480809926415229181136366306088766677371043354282148
Line 1750, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_fi/latest/run.log

  UVM_FATAL @  72027559 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  72027559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 19.aes_cipher_fi.33051187806002576239748896690648472592483522353544587829778805897438421177977
    Line 145, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004134737 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004134737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 62.aes_cipher_fi.72186073075600225053685896166335792675680984671600156475147642308609025719059
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/62.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025833974 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025833974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 6 failures:

Test aes_shadow_reg_errors_with_csr_rw has 5 failures.

1.aes_shadow_reg_errors_with_csr_rw.59060054304390688327186373552957005321757916590607871573459992616960451679245
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @ 128279889 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 128279889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_shadow_reg_errors_with_csr_rw.14304324102857171651142027626113927136736696347841172635304111603024399513018
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_ERROR @  33613733 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @  33613733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aes_shadow_reg_errors has 1 failures.

5.aes_shadow_reg_errors.69066501050990535406053717551063413274444110141226004753731686935314484961318
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_shadow_reg_errors/latest/run.log

  UVM_ERROR @ 101266998 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 101266998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 13.aes_control_fi.11663678803678981705608696162066818692659789317132659454405259335316747874735
    Line 147, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010500191 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010500191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_control_fi.101079088174668806527829484149367479376135519053314819072335121062761819540612
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008614752 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008614752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.102849627209626032852689554695246024859997224672184091100103494551180131155380
Line 1011, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3152069606 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3152069606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.103641995469115848276529072059878728377425960277838848935788152400312327715376
Line 1193, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1556537767 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1556537767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 23.aes_core_fi.26201675028246118138607515649371868090286932708580891972394266560467948169329
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011237289 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011237289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.aes_core_fi.104360501995341148921505361609814967873313051379534563708507911777450212474535
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003584112 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003584112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 8.aes_stress_all_with_rand_reset.5714371942792760577323874777238372977130111530455322695564606749423449390
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  19315186 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  19315186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.59014672170507339408417438505655573710244771772717259816875319547277304409131
    Line 503, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 709201806 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 709201806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:891) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.73664336681363208280293535356195659136095939445330321346992870125243953479835
    Line 333, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1357156761 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1357156761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 34.aes_fi.80276913979797381231293103871279660137148195928440990387653721682285346858791
    Line 7151, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/34.aes_fi/latest/run.log
```
  UVM_FATAL @  21732484 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  21732484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```