AON_TIMER Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	3.550s	569.214us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.750s	1.247ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	3.070s	316.658us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	22.580s	13.986ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.870s	476.435us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	3.130s	513.115us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	3.070s	316.658us	20	20	100.00
		aon_timer_csr_aliasing	2.870s	476.435us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.380s	357.202us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.420s	300.602us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	34.230s	27.938ms	15	15	100.00
V2	jump	aon_timer_jump	3.750s	736.155us	5	5	100.00
V2	stress_all	aon_timer_stress_all	3.520m	151.951ms	15	15	100.00
V2	intr_test	aon_timer_intr_test	2.630s	334.122us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.950s	452.982us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.950s	452.982us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.750s	1.247ms	5	5	100.00
		aon_timer_csr_rw	3.070s	316.658us	20	20	100.00
		aon_timer_csr_aliasing	2.870s	476.435us	5	5	100.00
		aon_timer_same_csr_outstanding	5.020s	2.663ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.750s	1.247ms	5	5	100.00
		aon_timer_csr_rw	3.070s	316.658us	20	20	100.00
		aon_timer_csr_aliasing	2.870s	476.435us	5	5	100.00
		aon_timer_same_csr_outstanding	5.020s	2.663ms	20	20	100.00
V2		TOTAL			125	125	100.00
V2S	tl_intg_err	aon_timer_sec_cm	14.530s	7.972ms	5	5	100.00
		aon_timer_tl_intg_err	24.860s	16.174ms	17	20	85.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	24.860s	16.174ms	17	20	85.00
V2S		TOTAL			22	25	88.00
V3	max_threshold	aon_timer_smoke_max_thold	3.260s	704.897us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	3.140s	697.616us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	8.750s	3.529ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.870s	637.511us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	13.420s	4.038ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	44.250s	22.981ms	15	15	100.00
V3		TOTAL			45	45	100.00
	Unmapped tests	aon_timer_alert_test	3.430s	484.450us	50	50	100.00
		TOTAL			312	315	99.05

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:665) [aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault has 3 failures:
  • Test aon_timer_tl_intg_err has 3 failures.

    • 2.aon_timer_tl_intg_err.56186557773392914601787263854126869909661037904605944566261907121354783344113
      Line 187, in log /nightly/runs/scratch/master/aon_timer-sim-vcs/2.aon_timer_tl_intg_err/latest/run.log

        UVM_FATAL @ 16173961433 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault
        UVM_INFO @ 16173961433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.aon_timer_tl_intg_err.72926530781913459190185373252442541106133742189558431966090315899229036415924
      Line 93, in log /nightly/runs/scratch/master/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest/run.log

        UVM_FATAL @ 11640498344 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault
        UVM_INFO @ 11640498344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.