CSRNG Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	293.248us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	64.247us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	73.018us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	17.000s	548.731us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	673.436us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	199.177us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	73.018us	20	20	100.00
		csrng_csr_aliasing	11.000s	673.436us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	27.000s	463.423us	198	200	99.00
V2	alerts	csrng_alert	56.817m	200.000ms	497	500	99.40
V2	err	csrng_err	22.000s	27.273us	500	500	100.00
V2	cmds	csrng_cmds	9.517m	46.877ms	50	50	100.00
V2	life cycle	csrng_cmds	9.517m	46.877ms	50	50	100.00
V2	stress_all	csrng_stress_all	29.400m	147.970ms	48	50	96.00
V2	intr_test	csrng_intr_test	6.000s	74.965us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	60.614us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	504.533us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	504.533us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	64.247us	5	5	100.00
		csrng_csr_rw	6.000s	73.018us	20	20	100.00
		csrng_csr_aliasing	11.000s	673.436us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	261.341us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	64.247us	5	5	100.00
		csrng_csr_rw	6.000s	73.018us	20	20	100.00
		csrng_csr_aliasing	11.000s	673.436us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	261.341us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	7.000s	292.098us	5	5	100.00
		csrng_tl_intg_err	18.000s	1.070ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	105.782us	50	50	100.00
		csrng_csr_rw	6.000s	73.018us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	56.817m	200.000ms	497	500	99.40
V2S	sec_cm_intersig_mubi	csrng_stress_all	29.400m	147.970ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	56.817m	200.000ms	497	500	99.40
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	29.400m	147.970ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	56.817m	200.000ms	497	500	99.40
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	18.000s	1.070ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
		csrng_sec_cm	7.000s	292.098us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	27.000s	463.423us	198	200	99.00
		csrng_err	22.000s	27.273us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.550m	3.432ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.78	98.63	96.69	99.97	97.42	92.08	100.00	97.36	90.82

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.88034845661588429119531784582363297927463853660153246897779965696787787276952
    Line 100, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202521428 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 202521428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.38943412482337541258658011199277348317049370781046429651592625638839242479226
    Line 102, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 413378546 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 413378546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

0.csrng_intr.101547864407342663939333934346075339453119483826966667579523209205696476983522
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 59681343 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  59681343 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  59681343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

99.csrng_intr.13710247704399297992584166473927404118700304964268071697123800329704943071812
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/99.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 70098537 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  70098537 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  70098537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

5.csrng_stress_all_with_rand_reset.109849076750694298248347704188700791596053403378244982719130937760271052034753
Line 114, in log /nightly/runs/scratch/master/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  19590554 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  19590554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.csrng_stress_all_with_rand_reset.109400784430208467996567919275534124471648990321132469679976871627566754557306
Line 126, in log /nightly/runs/scratch/master/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  18206695 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  18206695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

30.csrng_stress_all.66476520026259336809666675794438455072345030938631167167082885836359931860211
Line 153, in log /nightly/runs/scratch/master/csrng-sim-xcelium/30.csrng_stress_all/latest/run.log

  UVM_ERROR @ 317041777 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 317041777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.csrng_stress_all.3346157679216016498969802501692571639608959196912934607894513552820627188985
Line 138, in log /nightly/runs/scratch/master/csrng-sim-xcelium/45.csrng_stress_all/latest/run.log

  UVM_ERROR @  56550027 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  56550027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test csrng_alert has 2 failures.
  - 122.csrng_alert.82292235373084549384650224372805777246324351110857766474025503603001321593848
    Line 128, in log /nightly/runs/scratch/master/csrng-sim-xcelium/122.csrng_alert/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 148.csrng_alert.26622937047279080753096109995204064890167188307542261046432792372349882589598
    Line 128, in log /nightly/runs/scratch/master/csrng-sim-xcelium/148.csrng_alert/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test csrng_alert has 1 failures.
  - 80.csrng_alert.51453204687683367869205465591485655373528241013164821818339155110350096309980
    Log /nightly/runs/scratch/master/csrng-sim-xcelium/80.csrng_alert/latest/run.log
```
  Job timed out after 60 minutes
```