DMA Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	11.000s	1.198ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	13.000s	1.615ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	893.589us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	16.140us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	20.385us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	16.000s	4.627ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	10.000s	156.525us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	97.862us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	20.385us	20	20	100.00
		dma_csr_aliasing	10.000s	156.525us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.883m	11.356ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	7.717m	128.354ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	4.050m	53.157ms	2	3	66.67
V2	dma_generic_stress	dma_generic_stress	41.050m	486.807ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	7.717m	128.354ms	3	3	100.00
V2	dma_abort	dma_abort	17.000s	1.139ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	2.983m	43.492ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	10.676us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	84.451us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	84.451us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	16.140us	5	5	100.00
		dma_csr_rw	5.000s	20.385us	20	20	100.00
		dma_csr_aliasing	10.000s	156.525us	5	5	100.00
		dma_same_csr_outstanding	6.000s	136.723us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	16.140us	5	5	100.00
		dma_csr_rw	5.000s	20.385us	20	20	100.00
		dma_csr_aliasing	10.000s	156.525us	5	5	100.00
		dma_same_csr_outstanding	6.000s	136.723us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	dma_illegal_addr_range	dma_mem_enabled	30.000s	98.034us	5	5	100.00
		dma_generic_stress	41.050m	486.807ms	5	5	100.00
		dma_handshake_stress	7.717m	128.354ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	706.211us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.750m	17.911ms	5	5	100.00
		dma_longer_transfer	52.000s	3.185ms	5	5	100.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.85	97.09	95.27	97.05	96.52	84.02	82.76	97.66	40.59

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_memory_stress has 1 failures.

    • 0.dma_memory_stress.81767374367939622414354409437821499579178145818068910896465344951711020128896
      Log /nightly/runs/scratch/master/dma-sim-xcelium/0.dma_memory_stress/latest/run.log

        Job timed out after 60 minutes