EDN Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.520s 16.931us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.480s 48.287us 5 5 100.00
V1 csr_rw edn_csr_rw 2.500s 12.544us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.470s 424.315us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.980s 33.571us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.690s 24.520us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.500s 12.544us 20 20 100.00
edn_csr_aliasing 2.980s 33.571us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.008m 2.293ms 300 300 100.00
V2 csrng_commands edn_genbits 1.008m 2.293ms 300 300 100.00
V2 genbits edn_genbits 1.008m 2.293ms 300 300 100.00
V2 interrupts edn_intr 2.790s 21.796us 50 50 100.00
V2 alerts edn_alert 2.980s 493.469us 200 200 100.00
V2 errs edn_err 2.890s 37.009us 100 100 100.00
V2 disable edn_disable 2.540s 12.833us 50 50 100.00
edn_disable_auto_req_mode 2.850s 42.067us 50 50 100.00
V2 stress_all edn_stress_all 8.190s 312.315us 50 50 100.00
V2 intr_test edn_intr_test 2.420s 17.962us 50 50 100.00
V2 alert_test edn_alert_test 2.820s 58.860us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.630s 502.145us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.630s 502.145us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.480s 48.287us 5 5 100.00
edn_csr_rw 2.500s 12.544us 20 20 100.00
edn_csr_aliasing 2.980s 33.571us 5 5 100.00
edn_same_csr_outstanding 2.810s 503.669us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.480s 48.287us 5 5 100.00
edn_csr_rw 2.500s 12.544us 20 20 100.00
edn_csr_aliasing 2.980s 33.571us 5 5 100.00
edn_same_csr_outstanding 2.810s 503.669us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 13.810s 1.725ms 5 5 100.00
edn_tl_intg_err 12.990s 1.057ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.640s 17.722us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.980s 493.469us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 13.810s 1.725ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 13.810s 1.725ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 13.810s 1.725ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 13.810s 1.725ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.980s 493.469us 200 200 100.00
edn_sec_cm 13.810s 1.725ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.980s 493.469us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 12.990s 1.057ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.436m 5.128ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.04 98.33 94.29 97.02 93.60 96.36 99.78 92.94

Failure Buckets