HMAC Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.680s	271.453us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.660s	42.195us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.570s	137.489us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.860s	313.917us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.430s	546.801us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.363m	88.373ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.570s	137.489us	20	20	100.00
		hmac_csr_aliasing	8.430s	546.801us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.462m	6.348ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.490m	3.338ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.422m	18.043ms	30	30	100.00
		hmac_test_sha384_vectors	9.439m	60.952ms	75	75	100.00
		hmac_test_sha512_vectors	8.785m	13.358ms	75	75	100.00
		hmac_test_hmac256_vectors	15.870s	1.301ms	50	50	100.00
		hmac_test_hmac384_vectors	18.160s	419.742us	60	60	100.00
		hmac_test_hmac512_vectors	20.370s	388.506us	75	75	100.00
V2	burst_wr	hmac_burst_wr	32.780s	2.549ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	15.556m	5.557ms	10	10	100.00
V2	error	hmac_error	1.999m	4.814ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.002m	31.378ms	10	10	100.00
V2	save_and_restore	hmac_smoke	12.680s	271.453us	10	10	100.00
		hmac_long_msg	1.462m	6.348ms	10	10	100.00
		hmac_back_pressure	1.490m	3.338ms	25	25	100.00
		hmac_datapath_stress	15.556m	5.557ms	10	10	100.00
		hmac_burst_wr	32.780s	2.549ms	50	50	100.00
		hmac_stress_all	21.549m	54.148ms	25	25	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	12.680s	271.453us	10	10	100.00
		hmac_long_msg	1.462m	6.348ms	10	10	100.00
		hmac_back_pressure	1.490m	3.338ms	25	25	100.00
		hmac_datapath_stress	15.556m	5.557ms	10	10	100.00
		hmac_wipe_secret	2.002m	31.378ms	10	10	100.00
		hmac_test_sha256_vectors	4.422m	18.043ms	30	30	100.00
		hmac_test_sha384_vectors	9.439m	60.952ms	75	75	100.00
		hmac_test_sha512_vectors	8.785m	13.358ms	75	75	100.00
		hmac_test_hmac256_vectors	15.870s	1.301ms	50	50	100.00
		hmac_test_hmac384_vectors	18.160s	419.742us	60	60	100.00
		hmac_test_hmac512_vectors	20.370s	388.506us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	12.680s	271.453us	10	10	100.00
		hmac_long_msg	1.462m	6.348ms	10	10	100.00
		hmac_back_pressure	1.490m	3.338ms	25	25	100.00
		hmac_datapath_stress	15.556m	5.557ms	10	10	100.00
		hmac_burst_wr	32.780s	2.549ms	50	50	100.00
		hmac_error	1.999m	4.814ms	10	10	100.00
		hmac_wipe_secret	2.002m	31.378ms	10	10	100.00
		hmac_test_sha256_vectors	4.422m	18.043ms	30	30	100.00
		hmac_test_sha384_vectors	9.439m	60.952ms	75	75	100.00
		hmac_test_sha512_vectors	8.785m	13.358ms	75	75	100.00
		hmac_test_hmac256_vectors	15.870s	1.301ms	50	50	100.00
		hmac_test_hmac384_vectors	18.160s	419.742us	60	60	100.00
		hmac_test_hmac512_vectors	20.370s	388.506us	75	75	100.00
		hmac_stress_all	21.549m	54.148ms	25	25	100.00
V2	stress_all	hmac_stress_all	21.549m	54.148ms	25	25	100.00
V2	alert_test	hmac_alert_test	2.140s	28.105us	50	50	100.00
V2	intr_test	hmac_intr_test	2.260s	11.234us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.060s	710.970us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.060s	710.970us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.660s	42.195us	5	5	100.00
		hmac_csr_rw	2.570s	137.489us	20	20	100.00
		hmac_csr_aliasing	8.430s	546.801us	5	5	100.00
		hmac_same_csr_outstanding	4.260s	153.594us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.660s	42.195us	5	5	100.00
		hmac_csr_rw	2.570s	137.489us	20	20	100.00
		hmac_csr_aliasing	8.430s	546.801us	5	5	100.00
		hmac_same_csr_outstanding	4.260s	153.594us	20	20	100.00
V2		TOTAL			645	645	100.00
V2S	tl_intg_err	hmac_sec_cm	2.400s	469.587us	5	5	100.00
		hmac_tl_intg_err	6.060s	267.335us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.060s	267.335us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.680s	271.453us	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.570s	391.789us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	13.346m	52.900ms	25	25	100.00
V3		TOTAL			50	50	100.00
	Unmapped tests	hmac_directed	2.460s	21.036us	1	1	100.00
		TOTAL			786	786	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.85	99.84	97.20	100.00	100.00	99.84	98.79	47.30