I2C Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.671m	4.361ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	38.000s	3.316ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.190s	38.560us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.150s	21.359us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.780s	114.608us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.050s	170.888us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.450s	249.206us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.150s	21.359us	20	20	100.00
		i2c_csr_aliasing	3.050s	170.888us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	6.500s	292.710us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	41.066m	36.192ms	15	50	30.00
V2	host_maxperf	i2c_host_perf	29.330m	51.831ms	50	50	100.00
V2	host_override	i2c_host_override	2.230s	102.781us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.681m	42.279ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.315m	10.595ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.990s	745.734us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.020s	2.128ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.680s	481.251us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.269m	17.433ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	50.530s	4.479ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.600s	719.414us	18	50	36.00
V2	target_glitch	i2c_target_glitch	11.290s	7.520ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	27.571m	61.152ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	9.860s	953.813us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.286m	3.786ms	50	50	100.00
		i2c_target_intr_smoke	10.780s	5.149ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.660s	388.382us	50	50	100.00
		i2c_target_fifo_reset_tx	3.720s	296.372us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	21.582m	63.487ms	50	50	100.00
		i2c_target_stress_rd	1.286m	3.786ms	50	50	100.00
		i2c_target_intr_stress_wr	4.220m	21.861ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	12.010s	7.011ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.436m	2.122ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	9.860s	3.968ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	47.500s	10.042ms	27	50	54.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.650s	1.587ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.050s	259.420us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	29.330m	51.831ms	50	50	100.00
		i2c_host_perf_precise	3.859m	23.158ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	50.530s	4.479ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	9.650s	431.686us	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.260s	919.487us	50	50	100.00
		i2c_target_nack_acqfull_addr	5.120s	2.064ms	50	50	100.00
		i2c_target_nack_txstretch	3.490s	175.089us	39	50	78.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	23.550s	610.771us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.770s	3.219ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.300s	19.427us	50	50	100.00
V2	intr_test	i2c_intr_test	2.200s	45.601us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.770s	391.493us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.770s	391.493us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.190s	38.560us	5	5	100.00
		i2c_csr_rw	2.150s	21.359us	20	20	100.00
		i2c_csr_aliasing	3.050s	170.888us	5	5	100.00
		i2c_same_csr_outstanding	2.590s	30.323us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.190s	38.560us	5	5	100.00
		i2c_csr_rw	2.150s	21.359us	20	20	100.00
		i2c_csr_aliasing	3.050s	170.888us	5	5	100.00
		i2c_same_csr_outstanding	2.590s	30.323us	20	20	100.00
V2		TOTAL			1687	1792	94.14
V2S	tl_intg_err	i2c_tl_intg_err	4.080s	1.082ms	20	20	100.00
		i2c_sec_cm	2.370s	520.758us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	4.080s	1.082ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	24.550s	1.376ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.300s	434.340us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	33.580s	7.396ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1867	2042	91.43

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.22	97.35	89.74	74.17	73.21	94.34	98.52	90.17

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 43 failures:

Test i2c_host_mode_toggle has 15 failures.

0.i2c_host_mode_toggle.3676568938230835001783363104156125529335781441976831142399867566832127894323
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 240737031 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @25763

5.i2c_host_mode_toggle.27337409903573035956987663653423765278376918202468734764699608181653414215371
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 204544552 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @27131

... and 13 more failures.

Test i2c_host_stress_all has 28 failures.

3.i2c_host_stress_all.23470620207083674800915312565721845012963626470376395971506733499770674407092
Line 282, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 17491832874 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3742044

4.i2c_host_stress_all.38342756437899964568800461207225710399847458010853824199382719505569890767042
Line 117, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 42952549424 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3477312

... and 26 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 24 failures:
- Test i2c_target_unexp_stop has 24 failures.
  - 2.i2c_target_unexp_stop.24809511619252434105775534764424041581004724895403595279757274690103538319206
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 175206002 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 150 [0x96])
  UVM_INFO @ 175206002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.3028002448184013214971779341026774596539157869902893842553619727506645433488
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 149614289 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 203 [0xcb])
  UVM_INFO @ 149614289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 23 failures:
- Test i2c_target_hrst has 23 failures.
  - 0.i2c_target_hrst.75908922324127612990184346150941918376061867846032962111210783569712685408154
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10005056443 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10005056443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.20834307398186261619764186814757041775718786015620149699353540599559852948109
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 13772330089 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 13772330089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.

UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.66616576315219929690585701342459458103898348330644477932611234467537922283308
Line 93, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5589772727 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5589772727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.95889170913641845840157737094819577614705726085260816237866595191129968166708
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5330504790 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5330504790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 10 failures.

0.i2c_target_stress_all_with_rand_reset.106072575338059084420278181949916246366597793357312773092106382255275735671865
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1731125313 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1731125313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.110807093654740721999577577732182387946717401470185718080313497521773261506226
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 587457555 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 587457555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
- Test i2c_target_unexp_stop has 19 failures.
  - 1.i2c_target_unexp_stop.95902137580670755580413611789829936416073165408356634581123220892439139705649
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 128112386 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 128112386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.44785547939707395816818736898435592468442106191683645776980820441619641653403
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 134225286 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 134225286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 11 failures:

Test i2c_host_mode_toggle has 11 failures.

1.i2c_host_mode_toggle.2165701696356633613847317105616695778380953481722579063609598323322229906866
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 142412672 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

14.i2c_host_mode_toggle.79980412640464601323499346628165458717097804425234254672436841692656793114394
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  37900323 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 9 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 11 failures:
- Test i2c_target_nack_txstretch has 11 failures.
  - 6.i2c_target_nack_txstretch.50375918606772152359571801323500178368099663148831874624952152947211370602068
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 175089063 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 175089063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_nack_txstretch.97506099389566828248051293544021348108204314805662778092571385872497066738543
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 804144573 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 804144573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:

Test i2c_target_unexp_stop has 7 failures.

0.i2c_target_unexp_stop.38926796918952176819767331143431366863511176751237690429940584775906299466673
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 180845472 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 180845472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_unexp_stop.96751402833981413044529303719612189669877300096419997373264843058230563819642
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 278395276 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 278395276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

10.i2c_host_stress_all.35275252373739503963163414020493666989883100598382010936445247077180029497401
Line 154, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21058087515 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23668008

11.i2c_host_stress_all.13859805784220426807310545009933014752681478350238491571654123572424867121618
Line 291, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 84946601077 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21470452

... and 3 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
- Test i2c_host_mode_toggle has 5 failures.
  - 17.i2c_host_mode_toggle.46816356415138725436333623901395212646849651465720275583426285758516630046400
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  56172111 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x94f1114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  56172111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.i2c_host_mode_toggle.56975611871551867003820073836354927463706441485900014530966393074150704794311
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  30525810 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xf89b2714, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  30525810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
- Test i2c_target_stretch has 3 failures.
  - 5.i2c_target_stretch.36714654067077240866101434779580831676376115483340636094596648937684999772891
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10008548642 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10008548642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 35.i2c_target_stretch.110853911498196184162713384891346653287113096557125834757289416467792104204039
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/35.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10045776630 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10045776630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 5.i2c_host_stress_all.67315552916295545871899614520269129853248379687137225813857691235723581374605
    Log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 42.i2c_host_stress_all.56371619288890367241573801848290066673982525754165329125660976740557871483786
    Log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 15.i2c_target_tx_stretch_ctrl.1697975746327710182154558540603960617663286858604990347054758876843931612308
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 32.i2c_host_mode_toggle.88951759982820490055880630071892665202035922906011624787465734900572009239175
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/32.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```