KMAC/MASKED Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.887m	16.842ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.110s	124.714us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.270s	21.016us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.040s	779.738us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.110s	515.347us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.260s	168.979us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.270s	21.016us	20	20	100.00
		kmac_csr_aliasing	8.110s	515.347us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.990s	58.259us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.390s	131.502us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.677m	146.811ms	50	50	100.00
V2	burst_write	kmac_burst_write	21.666m	28.554ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.756m	76.216ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.555m	67.715ms	5	5	100.00
		kmac_test_vectors_sha3_384	29.309m	279.888ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.773m	30.522ms	5	5	100.00
		kmac_test_vectors_shake_128	44.142m	108.566ms	5	5	100.00
		kmac_test_vectors_shake_256	6.123m	36.257ms	5	5	100.00
		kmac_test_vectors_kmac	4.610s	96.654us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.360s	197.622us	5	5	100.00
V2	sideload	kmac_sideload	8.467m	224.875ms	50	50	100.00
V2	app	kmac_app	6.436m	13.338ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.345m	56.230ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.749m	17.355ms	50	50	100.00
V2	error	kmac_error	7.638m	61.897ms	50	50	100.00
V2	key_error	kmac_key_error	20.590s	9.839ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.070s	2.315ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.750s	6.236ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	19.290s	331.043us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.212m	9.065ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	24.000s	4.201ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.425m	99.483ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.980s	43.362us	50	50	100.00
V2	alert_test	kmac_alert_test	2.400s	67.468us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.120s	233.570us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.120s	233.570us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.110s	124.714us	5	5	100.00
		kmac_csr_rw	2.270s	21.016us	20	20	100.00
		kmac_csr_aliasing	8.110s	515.347us	5	5	100.00
		kmac_same_csr_outstanding	3.210s	329.625us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.110s	124.714us	5	5	100.00
		kmac_csr_rw	2.270s	21.016us	20	20	100.00
		kmac_csr_aliasing	8.110s	515.347us	5	5	100.00
		kmac_same_csr_outstanding	3.210s	329.625us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.620s	973.164us	15	20	75.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.620s	973.164us	15	20	75.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.620s	973.164us	15	20	75.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.620s	973.164us	15	20	75.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.700s	360.774us	5	20	25.00
V2S	tl_intg_err	kmac_sec_cm	1.746m	9.835ms	5	5	100.00
		kmac_tl_intg_err	4.540s	897.533us	18	20	90.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.540s	897.533us	18	20	90.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	24.000s	4.201ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.887m	16.842ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.467m	224.875ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.620s	973.164us	15	20	75.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.746m	9.835ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.746m	9.835ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.746m	9.835ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.887m	16.842ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	24.000s	4.201ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.746m	9.835ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.911m	27.352ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.887m	16.842ms	50	50	100.00
V2S		TOTAL			53	75	70.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.368m	2.539ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			912	940	97.02

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.55	99.23	94.47	99.89	80.99	97.05	99.37	97.86

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 13 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

0.kmac_shadow_reg_errors_with_csr_rw.107280820276227415002108805855003813055080604451164552705481020235813741628100
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 148836069 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 148836069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors_with_csr_rw.70734323103027899465674507748069434906880937977768839262233341634047849496869
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 132932134 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 132932134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_shadow_reg_errors has 5 failures.

5.kmac_shadow_reg_errors.56828496293233041715448803180985648441792911132600989713431183244138500659627
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  31803470 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  31803470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors.71819213371046071833077384318883860088725277366984128575060762545358705650000
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  28124729 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  28124729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.81147029232063130530936987937011452495450998668091627392906441150060574321833
    Line 129, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 263835933 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 263835933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.94271827947520206438639692669842197837092728032824811043198791937963074007026
    Line 193, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2668416221 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2668416221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 5 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.

4.kmac_shadow_reg_errors_with_csr_rw.36251151951586089894442020943023988334085992717348694624798583398916437779379
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  11120341 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  11120341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.kmac_shadow_reg_errors_with_csr_rw.54257866579908045098750905693552271353113662452755081327592415669732224904006
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  23230036 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  23230036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_tl_intg_err has 2 failures.

9.kmac_tl_intg_err.32625848697918213664414564140929442122941951289123813365363950298881959037815
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  32777552 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  32777552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_tl_intg_err.4485263912429095038877769109684429754568932504413869869646580803236861265374
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  86956101 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  86956101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:969) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 3 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 3 failures.
  - 1.kmac_shadow_reg_errors_with_csr_rw.92032834228465192841484297485793064934723629344914339768829108572898255050941
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  25096447 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @  25096447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.kmac_shadow_reg_errors_with_csr_rw.26229700497331605007709323721349967229385267847104429344295140089901665390259
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  20076158 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @  20076158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 5.kmac_shadow_reg_errors_with_csr_rw.89774010897110852970937291497472904799075433394441125389953061934404874006197
    Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  46801759 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (228 [0xe4] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
  UVM_INFO @  46801759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```