KMAC/UNMASKED Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.154m	15.134ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.540s	106.696us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.650s	25.861us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.750s	1.224ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.650s	832.075us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.820s	282.921us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.650s	25.861us	20	20	100.00
		kmac_csr_aliasing	10.650s	832.075us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.250s	76.988us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.960s	75.185us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.017h	533.966ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.517m	48.448ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.617m	428.682ms	5	5	100.00
		kmac_test_vectors_sha3_256	26.796m	100.935ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.195m	58.823ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.093m	307.309ms	5	5	100.00
		kmac_test_vectors_shake_128	35.483m	421.586ms	5	5	100.00
		kmac_test_vectors_shake_256	5.210m	15.577ms	5	5	100.00
		kmac_test_vectors_kmac	3.760s	116.144us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.860s	113.254us	5	5	100.00
V2	sideload	kmac_sideload	6.756m	39.252ms	50	50	100.00
V2	app	kmac_app	5.815m	263.625ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.043m	34.581ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.506m	52.296ms	50	50	100.00
V2	error	kmac_error	6.456m	75.450ms	50	50	100.00
V2	key_error	kmac_key_error	13.400s	1.534ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.542m	10.007ms	34	50	68.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.310s	6.489ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.480s	2.233ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.691m	43.103ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.730s	929.115us	50	50	100.00
V2	stress_all	kmac_stress_all	38.424m	1.312s	50	50	100.00
V2	intr_test	kmac_intr_test	2.370s	35.813us	50	50	100.00
V2	alert_test	kmac_alert_test	2.370s	19.525us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.660s	891.965us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.660s	891.965us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.540s	106.696us	5	5	100.00
		kmac_csr_rw	2.650s	25.861us	20	20	100.00
		kmac_csr_aliasing	10.650s	832.075us	5	5	100.00
		kmac_same_csr_outstanding	3.920s	342.931us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.540s	106.696us	5	5	100.00
		kmac_csr_rw	2.650s	25.861us	20	20	100.00
		kmac_csr_aliasing	10.650s	832.075us	5	5	100.00
		kmac_same_csr_outstanding	3.920s	342.931us	20	20	100.00
V2		TOTAL			724	740	97.84
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.000s	78.728us	11	20	55.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.000s	78.728us	11	20	55.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.000s	78.728us	11	20	55.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.000s	78.728us	11	20	55.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.890s	1.377ms	7	20	35.00
V2S	tl_intg_err	kmac_sec_cm	1.148m	5.095ms	5	5	100.00
		kmac_tl_intg_err	6.100s	821.244us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.100s	821.244us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.730s	929.115us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.154m	15.134ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.756m	39.252ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.000s	78.728us	11	20	55.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.148m	5.095ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.148m	5.095ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.148m	5.095ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.154m	15.134ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.730s	929.115us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.148m	5.095ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.467m	128.413ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.154m	15.134ms	50	50	100.00
V2S		TOTAL			49	75	65.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.598m	2.532ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			893	940	95.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.80	97.67	94.38	100.00	72.73	95.93	99.35	96.56

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 13 failures:

Test kmac_shadow_reg_errors has 9 failures.

4.kmac_shadow_reg_errors.39167238636845116157609190753108129293277995400683091713710421486458614339862
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  68975140 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  68975140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_shadow_reg_errors.83633486529876945642080463171320868539032329154094915061397670526725026040321
Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  17634190 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  17634190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

5.kmac_shadow_reg_errors_with_csr_rw.98168371464548046777997162455232069597462873757220384010732557043378807343165
Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  67892915 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  67892915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_shadow_reg_errors_with_csr_rw.41101345080473767464554461184572451513502991785829828232574032204105233241420
Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  19844081 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  19844081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 8 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

0.kmac_shadow_reg_errors_with_csr_rw.97040913974588343650089365544013113023665962111314771858713690925934514782894
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  43954326 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  43954326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.92144887501580534336630236930560142875154756082426532837460594733716695451800
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @   7638020 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @   7638020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_tl_intg_err has 4 failures.

0.kmac_tl_intg_err.68995841500572375286501341078343145808249249990277786987549262997206375970756
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  10923746 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  10923746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_tl_intg_err.8183806344637444925325474053285446574670536705724222015009098093415352725554
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @ 105604718 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @ 105604718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:969) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 5 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.
  - 3.kmac_shadow_reg_errors_with_csr_rw.35760220148420865434274949911568155062137215409189951660718925909516058924731
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 200668747 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @ 200668747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.kmac_shadow_reg_errors_with_csr_rw.19806802611931897525964454435699798136394959810178479176318389104405218886099
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  42460938 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @  42460938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
- Test kmac_sideload_invalid has 5 failures.
  - 6.kmac_sideload_invalid.41425122231096529994798342598251732230657335553669364620416208937559434628231
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10036120305 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x928b3000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10036120305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.kmac_sideload_invalid.19603288520744654022640353005101981651261206102828800760794320575416435527149
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10036590977 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9b37000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10036590977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:890) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.56342198286970907814197903628148126919972006322416695684797942234270110991274
    Line 128, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14816903675 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14816903675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.64652321205906401265530005559085608975861811410559818339253475176247260933601
    Line 92, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2296885883 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2296885883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 24.kmac_sideload_invalid.72696668847625451473973073113262024179252176843673833744571703546528267341366
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10032534403 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2ae49000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10032534403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.kmac_sideload_invalid.21632026248322977560069654608812248032864205508447889082623306761059806756512
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10094469871 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb5992000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10094469871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 44.kmac_sideload_invalid.65147745308733170205889715054144203541531596627507469142574893030069615821459
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10085550474 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x71987000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10085550474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 48.kmac_sideload_invalid.32201957786724343892036834876910958305290995423199791495277886246200023422696
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10096590470 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcdff2000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10096590470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 1.kmac_stress_all_with_rand_reset.11595399885874308653606379159173951433772250950140100104225567380836694467410
    Line 123, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1532266044 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1532266044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 3.kmac_sideload_invalid.97549514014666545574956188517833296351283612690876523087715991701704250722973
    Line 105, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10707964644 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd612a000, Comparison=CompareOpEq, exp_data=0x1, call_count=30)
  UVM_INFO @ 10707964644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 8.kmac_sideload_invalid.111877361245475580109155372282118277727152824610007352018956204756622711520372
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10195134023 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3a416000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10195134023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 16.kmac_sideload_invalid.25456994593969259218818682888132466548109867140478440877567163535424413360633
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/16.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10050068700 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x88f10000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10050068700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.67462665471370589889162259651537681800491371318747455877159866707848587933621
    Line 93, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10118943190 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe45ed000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
  UVM_INFO @ 10118943190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 34.kmac_sideload_invalid.76379276653968418605801953793092418557089786355154481026406552266147280951880
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10031954289 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x41cba000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10031954289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 37.kmac_sideload_invalid.91796380064311320072038434002732613356139400833151035122036004327464532613486
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10660454949 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2c6e8000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10660454949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 42.kmac_sideload_invalid.54679320620399910706561752696950510865963410748227413449007641513739695098954
    Line 94, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10145094781 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaacf6000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
  UVM_INFO @ 10145094781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```