MBX Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 1.900m 3.202ms 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 5.000s 16.023us 5 5 100.00
V1 csr_rw mbx_csr_rw 5.000s 14.724us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 6.000s 113.878us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 5.000s 20.256us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 5.000s 1.032us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 5.000s 14.724us 20 20 100.00
mbx_csr_aliasing 5.000s 20.256us 5 5 100.00
V1 TOTAL 37 57 64.91
V2 mbx_stress mbx_stress 1.067m 450.812us 2 2 100.00
mbx_stress_zero_delays 1.517m 4.201ms 2 2 100.00
V2 mbx_imbx_oob mbx_imbx_oob 57.000s 673.427us 2 2 100.00
V2 alert_test mbx_alert_test 27.000s 134.022us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 5.000s 3.940us 0 20 0.00
V2 tl_d_illegal_access mbx_tl_errors 5.000s 3.940us 0 20 0.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 5.000s 16.023us 5 5 100.00
mbx_csr_rw 5.000s 14.724us 20 20 100.00
mbx_csr_aliasing 5.000s 20.256us 5 5 100.00
mbx_same_csr_outstanding 5.000s 20.412us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 5.000s 16.023us 5 5 100.00
mbx_csr_rw 5.000s 14.724us 20 20 100.00
mbx_csr_aliasing 5.000s 20.256us 5 5 100.00
mbx_same_csr_outstanding 5.000s 20.412us 20 20 100.00
V2 TOTAL 76 96 79.17
V2S tl_intg_err mbx_sec_cm 31.000s 38.272us 5 5 100.00
mbx_tl_intg_err 5.000s 178.501us 0 20 0.00
V2S TOTAL 5 25 20.00
TOTAL 118 178 66.29

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
89.03 96.95 92.42 96.87 82.31 76.56 -- 97.08 63.09

Failure Buckets