RV_TIMER Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	36.431m	79.786ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.190s	97.907us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.190s	49.196us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.860s	841.282us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.440s	127.860us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	3.040s	32.626us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.190s	49.196us	20	20	100.00
		rv_timer_csr_aliasing	2.440s	127.860us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	30.948m	218.754ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.421m	725.313ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	23.156m	753.515ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	23.156m	753.515ms	50	50	100.00
V2	stress	rv_timer_stress_all	41.821m	516.460ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.260s	11.350us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.380s	271.728us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.380s	271.728us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.190s	97.907us	5	5	100.00
		rv_timer_csr_rw	2.190s	49.196us	20	20	100.00
		rv_timer_csr_aliasing	2.440s	127.860us	5	5	100.00
		rv_timer_same_csr_outstanding	2.500s	70.086us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.190s	97.907us	5	5	100.00
		rv_timer_csr_rw	2.190s	49.196us	20	20	100.00
		rv_timer_csr_aliasing	2.440s	127.860us	5	5	100.00
		rv_timer_same_csr_outstanding	2.500s	70.086us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	2.310s	275.806us	5	5	100.00
		rv_timer_tl_intg_err	3.060s	103.325us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.060s	103.325us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.286m	5.567ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			587	620	94.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.74	100.00	99.36	100.00	--	100.00	100.00	99.09

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

  • Test rv_timer_stress_all_with_rand_reset has 30 failures.

    • 1.rv_timer_stress_all_with_rand_reset.84114316004184122841848601266195561823961548340746473725720433741071757851262
      Line 91, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1798861494 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1798861494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.rv_timer_stress_all_with_rand_reset.103902691875796403472881718190398633511519106681779783221681780522055229529089
      Line 79, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 955812661 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10014 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 955812661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 28 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test rv_timer_disabled has 2 failures.

    • 4.rv_timer_disabled.72794110463771856099358065445538690408650829615219840043878780762669471055957
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.rv_timer_disabled.63656512387108089105673689262690098917377494887633428080250764000382705297348
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/12.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:794) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 6.rv_timer_stress_all_with_rand_reset.9188865132194892048247946121695407571377734014414530193665517576600593462633
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  30430682 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @  30430682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---