SPI_HOST Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.883m	45.203ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.671us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	15.849us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	165.465us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	53.579us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	32.474us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	15.849us	20	20	100.00
		spi_host_csr_aliasing	5.000s	53.579us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	24.140us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	22.592us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	52.556us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.017m	62.097ms	49	50	98.00
		spi_host_error_cmd	5.000s	18.340us	50	50	100.00
		spi_host_event	4.967m	50.595ms	50	50	100.00
V2	clock_rate	spi_host_speed	25.000s	584.267us	50	50	100.00
V2	speed	spi_host_speed	25.000s	584.267us	50	50	100.00
V2	chip_select_timing	spi_host_speed	25.000s	584.267us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.567m	7.791ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	850.166us	50	50	100.00
V2	cpol_cpha	spi_host_speed	25.000s	584.267us	50	50	100.00
V2	full_cycle	spi_host_speed	25.000s	584.267us	50	50	100.00
V2	duplex	spi_host_smoke	6.883m	45.203ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	6.883m	45.203ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.150m	8.808ms	50	50	100.00
V2	spien	spi_host_spien	1.567m	7.237ms	50	50	100.00
V2	stall	spi_host_status_stall	6.067m	10.217ms	44	50	88.00
V2	Idlecsbactive	spi_host_idlecsbactive	48.000s	2.011ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.017m	62.097ms	49	50	98.00
V2	alert_test	spi_host_alert_test	5.000s	53.527us	50	50	100.00
V2	intr_test	spi_host_intr_test	9.000s	20.500us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	8.000s	263.309us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	8.000s	263.309us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.671us	5	5	100.00
		spi_host_csr_rw	5.000s	15.849us	20	20	100.00
		spi_host_csr_aliasing	5.000s	53.579us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	52.738us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.671us	5	5	100.00
		spi_host_csr_rw	5.000s	15.849us	20	20	100.00
		spi_host_csr_aliasing	5.000s	53.579us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	52.738us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	88.737us	20	20	100.00
		spi_host_sec_cm	5.000s	72.695us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	88.737us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	47.667m	100.004ms	3	10	30.00
		TOTAL			826	840	98.33

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.29	96.74	93.21	98.70	94.71	88.02	100.00	96.86	91.56

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
- Test spi_host_upper_range_clkdiv has 3 failures.
  - 3.spi_host_upper_range_clkdiv.24281170938104852385639313783541216545558748735418321296444220852629638563838
    Line 164, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002756434 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xed4e7754, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100002756434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.spi_host_upper_range_clkdiv.52859069532105720836806612346269091718273493549707121563777618142170008104612
    Line 133, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002589560 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xef86f694, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100002589560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85) has 2 failures:
- Test spi_host_status_stall has 2 failures.
  - 26.spi_host_status_stall.58638274393905846542432483883213372928483031840160604882233680708598575577051
    Line 733, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/26.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10508288339 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x50b1b794, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
  UVM_INFO @ 10508288339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.spi_host_status_stall.106351109368080978180587577742163578264791104122332183638689519946061356593683
    Line 729, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/41.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10433072770 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x6ed2db14, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
  UVM_INFO @ 10433072770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 1.spi_host_upper_range_clkdiv.87793524674033071062125057479776734306324694678318262602750312284249951443586
    Line 137, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002819549 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe596b7d4, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 100002819549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 2.spi_host_upper_range_clkdiv.88757143319311048771675812015531625673253435288604450097102618119251395203896
    Line 123, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100002174653 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x430c6654, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 100002174653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 3.spi_host_status_stall.102605355234074713106471791368789083092974030027658407187322017206990616741164
    Line 707, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10224353064 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x40301254, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
  UVM_INFO @ 10224353064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 7.spi_host_upper_range_clkdiv.100092192219401819703692645765411805568086488599531889585558395090291620429335
    Log /nightly/runs/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 9.spi_host_upper_range_clkdiv.51282811716274564138327389044337362600341738094768491198269410737862232288732
    Line 138, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100010432772 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xecbbb614, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 100010432772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=79) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 17.spi_host_status_stall.96511707418838105868993431937153030484195075045167712053419053959499216613988
    Line 706, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10217238743 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x24a2cd94, Comparison=CompareOpEq, exp_data=0x1, call_count=79)
  UVM_INFO @ 10217238743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=87) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 30.spi_host_status_stall.69799538096745400830530936999317119111355234418739396251663355859179953369989
    Line 725, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/30.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 11378361410 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x82417d4, Comparison=CompareOpEq, exp_data=0x1, call_count=87)
  UVM_INFO @ 11378361410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

39.spi_host_status_stall.27038903969625648054167902778096039211136797532153442812886442538053648000373
Line 792, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/39.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 1242734622 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 1242734622 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=1242735000 ps
  UVM_INFO @ 1242734622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=64) has 1 failures:
- Test spi_host_overflow_underflow has 1 failures.
  - 48.spi_host_overflow_underflow.46351535160428803512838731660604424710517716558559050314591045067964564950066
    Line 99, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/48.spi_host_overflow_underflow/latest/run.log
```
  UVM_FATAL @ 62096779859 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3c32a314, Comparison=CompareOpEq, exp_data=0x0, call_count=64)
  UVM_INFO @ 62096779859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```