UART Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.100s	5.781ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	4.590s	1.033ms	5	5	100.00
V1	csr_rw	uart_csr_rw	2.370s	54.621us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	4.170s	1.025ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.470s	25.825us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.640s	98.148us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.370s	54.621us	20	20	100.00
		uart_csr_aliasing	2.470s	25.825us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.284m	123.490ms	50	50	100.00
V2	parity	uart_smoke	38.100s	5.781ms	50	50	100.00
		uart_tx_rx	4.284m	123.490ms	50	50	100.00
V2	parity_error	uart_intr	5.881m	145.324ms	50	50	100.00
		uart_rx_parity_err	9.281m	229.382ms	50	50	100.00
V2	watermark	uart_tx_rx	4.284m	123.490ms	50	50	100.00
		uart_intr	5.881m	145.324ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.030m	217.726ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.008m	163.540ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	6.773m	243.751ms	300	300	100.00
V2	rx_frame_err	uart_intr	5.881m	145.324ms	50	50	100.00
V2	rx_break_err	uart_intr	5.881m	145.324ms	50	50	100.00
V2	rx_timeout	uart_intr	5.881m	145.324ms	50	50	100.00
V2	perf	uart_perf	23.248m	36.971ms	50	50	100.00
V2	sys_loopback	uart_loopback	22.360s	15.346ms	50	50	100.00
V2	line_loopback	uart_loopback	22.360s	15.346ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.832m	132.151ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.512m	39.635ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	32.390s	6.385ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.127m	6.927ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.442m	152.645ms	49	50	98.00
V2	stress_all	uart_stress_all	33.939m	281.667ms	50	50	100.00
V2	alert_test	uart_alert_test	2.220s	16.009us	50	50	100.00
V2	intr_test	uart_intr_test	2.330s	35.503us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	4.280s	293.217us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	4.280s	293.217us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	4.590s	1.033ms	5	5	100.00
		uart_csr_rw	2.370s	54.621us	20	20	100.00
		uart_csr_aliasing	2.470s	25.825us	5	5	100.00
		uart_same_csr_outstanding	2.520s	16.739us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	4.590s	1.033ms	5	5	100.00
		uart_csr_rw	2.370s	54.621us	20	20	100.00
		uart_csr_aliasing	2.470s	25.825us	5	5	100.00
		uart_same_csr_outstanding	2.520s	16.739us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	2.510s	76.997us	5	5	100.00
		uart_tl_intg_err	3.050s	95.099us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.050s	95.099us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.643m	6.106ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1318	1320	99.85

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.18	98.25	91.55	--	98.15	100.00	99.50

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 11.uart_long_xfer_wo_dly.33764834855421932270956947305845680036027799550627127385724229840169125780301
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @ 1293340516 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_ERROR @ 1304575900 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_ERROR @ 3197885164 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_INFO @ 5353549468 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
        UVM_INFO @ 15109627516 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/10
      

• UVM_ERROR (cip_base_vseq.sv:890) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 27.uart_stress_all_with_rand_reset.21906346221107005769059469472831445164518162810409296746359574180736126396280
      Line 139, in log /nightly/runs/scratch/master/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9905515822 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 9905521403 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 9905521403 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/10
        UVM_INFO @ 9905555822 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2