CHIP Simulation Results

Sunday March 30 2025 00:05:47 UTC

GitHub Revision: `056762e2b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.730m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.730m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	50.450s		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	49.442s		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	45.489s		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	32.434s		0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	32.434s		0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	32.434s		0	3	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	2.810m		0	3	0.00
		chip_sw_example_manufacturer	3.166m		0	3	0.00
		chip_sw_example_concurrency	2.510m		0	3	0.00
		chip_sw_uart_smoketest_signed	1.065s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	17.640s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	18.420s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	18.420s		0	3	0.00
V1	xbar_smoke	xbar_smoke	38.540s	67.509us	100	100	100.00
V1		TOTAL			100	156	64.10
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.197m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	37.452s		0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	33.445s		0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	41.480s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	39.476s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	45.494s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	43.487s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	13.809s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	13.809s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.014m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.475m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.542m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.542m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.211m	4.239ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.712m	3.879ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	19.098s		0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	20.097s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.082s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	19.084m	30.074ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	18.278s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	18.612s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	18.612s		0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	14.511s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.501s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.501s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	23.869s		0	5	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	25.269s		0	3	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	26.365s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	1.006s		0	3	0.00
		chip_sw_aes_idle	36.259s		0	3	0.00
		chip_sw_hmac_enc_idle	14.583s		0	3	0.00
		chip_sw_kmac_idle	41.709s		0	3	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.074s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	10.093s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	10.152s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	10.169s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.165s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.011m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	33.263s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	41.568s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.150s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.165s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.011m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	33.263s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	41.568s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	21.719s		0	3	0.00
		chip_sw_aes_enc_jitter_en	36.247s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	17.716s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	14.580s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.593s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.060s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	28.298s		0	3	0.00
		chip_sw_clkmgr_jitter	25.161s		0	3	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	25.137s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	25.142s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	12.080s		0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.083m		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	26.243s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	13.192s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	26.321s		0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	17.133s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.077s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	25.160s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	26.180s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	2.582m		0	100	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	46.399s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	14.501s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	21.718s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	46.399s		0	3	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	42.380s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.312s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	41.349s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	41.347s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	23.292s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	2.582m		0	100	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	19.098s		0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	53.420s		0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	54.431s		0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	54.436s		0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	54.434s		0	3	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	2.582m		0	100	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.504s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	34.459s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	2.582m		0	100	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	25.269s		0	3	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	40.552s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	54.436s		0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	29.353s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	48.049s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	21.690s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	22.756s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	21.694s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	36.248s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	34.459s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	29.231s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	15.449s		0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	30.269s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.254s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	25.149s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	26.245s		0	3	0.00
		chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	14.584s		0	3	0.00
		chip_sw_rom_ctrl_integrity_check	25.085s		0	3	0.00
		chip_sw_sram_ctrl_execution_main	10.013s		0	3	0.00
		chip_prim_tl_access	20.557m	29.878ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.165s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.150s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.011m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	33.263s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	41.568s		0	3	0.00
		chip_rv_dm_lc_disabled	19.084m	30.074ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	1.077s		0	3	0.00
		chip_sw_aes_enc_jitter_en	36.247s		0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	34.881s		0	3	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	36.259s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	32.228s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	14.580s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	14.583s		0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.006s		0	3	0.00
		chip_sw_kmac_mode_kmac	14.591s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.060s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	14.584s		0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	15.252s		0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	32.440s		0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	41.709s		0	3	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	20.757s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	20.757s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.436s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	29.104s		0	3	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.418s		0	3	0.00
		chip_sw_edn_entropy_reqs	17.711s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	14.584s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.593s		0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	23.870s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	21.719s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	1.006s		0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	1.006s		0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	1.006s		0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	26.160s		0	3	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	25.085s		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	25.085s		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	15.671s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	28.298s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.013s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	2.582m		0	100	0.00
		chip_sw_data_integrity_escalation	1.542m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	26.160s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation	14.584s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	15.671s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	29.818s		0	3	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	26.160s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation	14.584s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	15.671s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	29.818s		0	3	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.095s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	29.231s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	30.269s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	17.254s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	25.149s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	26.245s		0	3	0.00
		chip_sw_lc_ctrl_transition	54.405s		0	15	0.00
		chip_prim_tl_access	20.557m	29.878ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	20.557m	29.878ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	56.584s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	54.396s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.077s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	21.719s		0	3	0.00
		chip_sw_aes_enc_jitter_en	36.247s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	17.716s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	14.580s		0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	14.593s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.060s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	28.298s		0	3	0.00
		chip_sw_clkmgr_jitter	25.161s		0	3	0.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	10.012s		0	5	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.012s		0	5	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.012s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	10.013s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.012s		0	3	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	17.259s		0	3	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	17.259s		0	3	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	15.740s		0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	32.246s		0	3	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	21.715s		0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	1.068s		0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	36.237s		0	3	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	57.895s		0	3	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	29.818s		0	3	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	53.420s		0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	53.420s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	20.443s		0	3	0.00
		chip_sw_aon_timer_smoketest	33.872s		0	3	0.00
		chip_sw_clkmgr_smoketest	1.042s		0	3	0.00
		chip_sw_csrng_smoketest	32.880s		0	3	0.00
		chip_sw_gpio_smoketest	1.035s		0	3	0.00
		chip_sw_hmac_smoketest	15.093s		0	3	0.00
		chip_sw_kmac_smoketest	47.389s		0	3	0.00
		chip_sw_otbn_smoketest	1.041s		0	3	0.00
		chip_sw_otp_ctrl_smoketest	1.042s		0	3	0.00
		chip_sw_rv_plic_smoketest	1.065s		0	3	0.00
		chip_sw_rv_timer_smoketest	30.185s		0	3	0.00
		chip_sw_rstmgr_smoketest	58.552s		0	3	0.00
		chip_sw_sram_ctrl_smoketest	1.062s		0	3	0.00
		chip_sw_uart_smoketest	1.075s		0	3	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	1.066s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	1.065s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.197m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	1.066s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	54.411s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	54.414s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	54.417s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	54.420s		0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	53.283s		0	3	0.00
		chip_rv_dm_lc_disabled	19.084m	30.074ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	54.422s		0	3	0.00
		chip_sw_lc_walkthrough_prod	54.425s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	54.428s		0	3	0.00
		chip_sw_lc_walkthrough_rma	54.433s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	53.283s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	54.431s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	54.431s		0	3	0.00
		rom_volatile_raw_unlock	27.303s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	31.754s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	50.448s		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	25.433s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.936m	4.459ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.936m	4.459ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	18.420s		0	3	0.00
		chip_same_csr_outstanding	17.920s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	18.420s		0	3	0.00
		chip_same_csr_outstanding	17.920s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.911m	518.979us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	16.700s	13.912us	100	100	100.00
		xbar_smoke_large_delays	10.236m	2.803ms	100	100	100.00
		xbar_smoke_slow_rsp	11.338m	2.213ms	100	100	100.00
		xbar_random_zero_delays	2.391m	77.063us	100	100	100.00
		xbar_random_large_delays	35.325m	11.047ms	100	100	100.00
		xbar_random_slow_rsp	53.643m	12.600ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.843m	182.830us	100	100	100.00
		xbar_error_and_unmapped_addr	2.677m	223.898us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.787m	540.038us	100	100	100.00
		xbar_error_and_unmapped_addr	2.677m	223.898us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.263m	885.587us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.924m	21.491ms	69	100	69.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	4.364m	486.268us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	36.804m	4.971ms	100	100	100.00
		xbar_stress_all_with_error	32.690m	4.564ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	57.651m	5.737ms	98	100	98.00
		xbar_stress_all_with_reset_error	55.538m	6.138ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.181s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	15.244s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	25.331s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	40.201s		0	3	0.00
		rom_e2e_asm_init_dev	1.041s		0	3	0.00
		rom_e2e_asm_init_prod	14.163s		0	3	0.00
		rom_e2e_asm_init_prod_end	25.294s		0	3	0.00
		rom_e2e_asm_init_rma	27.336s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	26.111s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	27.294s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	25.250s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	25.294s		0	3	0.00
V2		TOTAL			1673	2449	68.31
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	23.868s		0	3	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	34.780s		0	3	0.00
V2S		TOTAL			0	6	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.014s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	2.582m		0	100	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	56.581s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	43.090s	10.100us	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	26.876s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0			0	1	0.00
		rom_e2e_jtag_inject_dev			0	1	0.00
		rom_e2e_jtag_inject_rma			0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.058s		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	2.080m		0	3	0.00
		chip_sw_dma_inline_hashing	14.216s		0	3	0.00
		chip_sw_dma_abort	13.180s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	25.284s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	25.252s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	26.329s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	24.438s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	28.739s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	26.626s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	27.728s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	15.351s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.429s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	1.042s		0	3	0.00
		chip_sw_mbx_smoketest	43.415s		0	3	0.00
		TOTAL			1773	2673	66.33

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
55.30	58.67	54.99	42.50	--	53.97	40.69	80.99

Failure Buckets

Job returned non-zero exit code has 599 failures:

Test chip_sw_example_rom has 2 failures.

0.chip_sw_example_rom.12864527076208203827006906143918247496671721156937496939739543954184942889328
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (5f4d14)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (d87967)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 141.286s, Critical Path: 0.09s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

2.chip_sw_example_rom.108250008266735694589563814363961354048337820048697216393180843470954278981845
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 108250008266735694589563814363961354048337820048697216393180843470954278981845' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=639144149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.639144149' seed=108250008266735694589563814363961354048337820048697216393180843470954278981845 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images=//sw/device/tests:example_test_from_rom:0:test_in_rom uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

Test chip_sw_example_manufacturer has 2 failures.

0.chip_sw_example_manufacturer.72258472817148420827342214769256191331651867101563788698738614953176481957252
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Another command (pid=2554330) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2553690) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2553447) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2556699) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2556454) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2566993) is running. Waiting for it to complete on the server (server_pid=2550799)...

  Server terminated abruptly (error code: 14, error message: 'Socket closed', log file: '/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/server/jvm.out')

  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

2.chip_sw_example_manufacturer.15999014097874035408047062300549173888693076618983182509368560696773433843877
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 15999014097874035408047062300549173888693076618983182509368560696773433843877' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_manufacturer/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3105579173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3105579173' seed=15999014097874035408047062300549173888693076618983182509368560696773433843877 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='@manufacturer_test_hooks//:example_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

Test chip_sw_example_concurrency has 2 failures.

0.chip_sw_example_concurrency.69289736586745904194405560410639289732282506789540993673289419393449183481119
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

  [707 / 1,834] Action hw/top/ast_regs.h; 3s processwrapper-sandbox ... (95 actions, 94 running)
  Target //sw/device/tests:example_concurrency_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: /nightly/runs/opentitan/sw/device/tests/BUILD:1608:15 Middleman _middlemen/sw_Sdevice_Stests_Sexample_Uconcurrency_Utest_Usim_Udv.bash-runfiles failed: (Exit -1): riscv32-unknown-elf-ar failed: error executing CppArchive command (from target //sw/device/silicon_creator/lib/base:static_critical_sec_mmio) external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/bin/riscv32-unknown-elf-ar rcsD ... (remaining 2 arguments skipped)

  Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging
  INFO: Elapsed time: 133.756s, Critical Path: 4.60s
  INFO: 802 processes: 615 internal, 187 processwrapper-sandbox.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

2.chip_sw_example_concurrency.12263862140527660415768373997639829938712742593623304057397165720691597276383
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 12263862140527660415768373997639829938712742593623304057397165720691597276383' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_example_concurrency/latest run_opts='+sw_build_device=sim_dv +sw_images=example_concurrency_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2051699935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.2051699935' seed=12263862140527660415768373997639829938712742593623304057397165720691597276383 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests:example_concurrency_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

Test chip_sw_all_escalation_resets has 99 failures.

0.chip_sw_all_escalation_resets.83125033773720699828611096525450233061575573163283207840123712756191709242778
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

  Another command (pid=2554330) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2553530) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2553447) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2567105) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2556454) is running. Waiting for it to complete on the server (server_pid=2550799)...
  Another command (pid=2566993) is running. Waiting for it to complete on the server (server_pid=2550799)...

  Server terminated abruptly (error code: 14, error message: 'Socket closed', log file: '/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/server/jvm.out')

  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

2.chip_sw_all_escalation_resets.81566912039038347262830728134070113361334732134549595864968746298097925851408
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 81566912039038347262830728134070113361334732134549595864968746298097925851408' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=143362320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.143362320' seed=81566912039038347262830728134070113361334732134549595864968746298097925851408 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_all_escalation_resets_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 97 more failures.

Test chip_sw_rstmgr_rst_cnsty_escalation has 2 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.29901831569429533689417683970555112801888739582939171598716206966261145566756
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

  ERROR: /nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/external/rules_rust_bindgen++rust_ext+rules_rust_bindgen_deps__unicode-width-0.2.0/BUILD.bazel:14:20: ExtractCargoTomlEnvVars external/rules_rust_bindgen++rust_ext+rules_rust_bindgen_deps__unicode-width-0.2.0/cargo_toml_env_vars.env [for tool] failed: (Exit 1): cargo_toml_variable_extractor failed: error executing ExtractCargoTomlEnvVars command (from target @@rules_rust_bindgen++rust_ext+rules_rust_bindgen_deps__unicode-width-0.2.0//:cargo_toml_env_vars) bazel-out/k8-opt-exec-ST-fdd1730c120c/bin/external/rules_rust+/cargo/cargo_toml_variable_extractor/cargo_toml_variable_extractor ... (remaining 2 arguments skipped)

  Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging
  src/main/tools/process-wrapper-legacy.cc:66: "fork": Resource temporarily unavailable
  Target //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  INFO: Elapsed time: 107.184s, Critical Path: 27.86s
  INFO: 1001 processes: 721 action cache hit, 91 internal, 910 processwrapper-sandbox.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

2.chip_sw_rstmgr_rst_cnsty_escalation.91029219886393152616149415332066991193087086001309196776435301292521574923544
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

        --mmap-def /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_mmap.hjson \
        --img-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_darjeeling/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 91029219886393152616149415332066991193087086001309196776435301292521574923544' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest run_opts='+bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:6:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2313190680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2313190680' seed=91029219886393152616149415332066991193087086001309196776435301292521574923544 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='--//hw/top=darjeeling --//hw/top=darjeeling' sw_images='//sw/device/tests/sim_dv:all_escalation_resets_test:6:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_rstmgr_cnsty_fault_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 186 more tests.

Job timed out after * minutes has 258 failures:
- Test chip_sw_otbn_randomness has 2 failures.
  - 0.chip_sw_otbn_randomness.102263336811991489087982599105755955227844041083688153654389737494202854534890
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otbn_randomness/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_otbn_randomness.70995301013047882073271669001128395847951594891938140460648867599082372158815
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_otbn_randomness/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_rv_core_ibex_nmi_irq has 2 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.84139766671497560196181303464014340606282030827589527953226540344054677232972
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.111550091370852773844637149049911560227863568372855453410790781164313761020818
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_aes_enc has 2 failures.
  - 0.chip_sw_aes_enc.48881953855055671327105688281031876937754448580471536565624595220920824164022
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_aes_enc.34375794029364952580467813532124966943705572479477967793527541194902389393471
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_hmac_enc has 2 failures.
  - 0.chip_sw_hmac_enc.307498067181151687493583555955256491647725357143922720742782676175136799466
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_hmac_enc.54513783499459816556773655856736854190797317121246148653747649360340655965565
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_kmac_mode_cshake has 2 failures.
  - 0.chip_sw_kmac_mode_cshake.62666423823154121235070246459153250580699102173502454250731974029573319146743
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_kmac_mode_cshake.111647974414700532413497800142822711384131462785311422993217591800968242274816
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_cshake/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 215 more tests.

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 14 failures:

Test chip_tl_errors has 14 failures.

2.chip_tl_errors.454586476072740006804422177450136803828466669566205925512867633275324808410
Line 266, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4740.762872 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4740.762872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.chip_tl_errors.62371290488396615693564183785506162442250674320580892068135428210760896871327
Line 257, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3960.179820 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3960.179820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 6 failures:
- Test chip_csr_bit_bash has 2 failures.
  - 0.chip_csr_bit_bash.86804129590270057791201948878194618740019853933194157072568843323862004135786
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.41562732208080652876806639924381603967758838685654625610753127958416037687890
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 2 failures.
  - 0.chip_csr_aliasing.97139817286400495358784430331015149525620955616148020716866654833453906793779
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.66164332881716813243937296684658180201104572741546890932337121740379763562537
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 2 failures.
  - 0.chip_same_csr_outstanding.114207578702553406914415108121009868193107310612645389099818119388923058341488
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.69883548791318117425113569213169417279005628225901930312131415269966497301662
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 5 failures:

Test chip_jtag_csr_rw has 2 failures.

0.chip_jtag_csr_rw.67097947895946304612596943663902867750633011027812628058449796592408946719431
Line 6149, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4239.347520 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: 'h30480000  a_data: 'h99deb907  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h248f3  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4239.347520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.47775630376161723206132277870292179515241684925582446049856645301497694763312
Line 6149, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4398.507717 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: 'h30480000  a_data: 'h4fec27bb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h0  a_user: 'h26932  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4398.507717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.2630617521822268840545460559159262564579237438015543572528457001870729839926
Line 6149, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3879.081675 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: 'h30480000  a_data: 'hffa839cd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h0  a_user: 'h2696b  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3879.081675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.94465910180754927948374337736926435166738649934527772505293588504100877182195
Line 6149, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4281.178550 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: 'h30480000  a_data: 'h95b298a3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1c  a_opcode: 'h0  a_user: 'h26903  d_param: 'h0  d_source: 'h1c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4281.178550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file all_escalation_resets_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.109778972787614759338993385210593306727618588213030279989537558172987941599036
    Line 483, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file all_escalation_resets_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36571) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: