AES/MASKED Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	327.512us	1	1	100.00
V1	smoke	aes_smoke	9.000s	571.742us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	74.602us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	96.341us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	589.674us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	129.793us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	95.604us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	96.341us	20	20	100.00
		aes_csr_aliasing	6.000s	129.793us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	571.742us	50	50	100.00
		aes_config_error	13.000s	2.213ms	50	50	100.00
		aes_stress	10.000s	297.600us	50	50	100.00
V2	key_length	aes_smoke	9.000s	571.742us	50	50	100.00
		aes_config_error	13.000s	2.213ms	50	50	100.00
		aes_stress	10.000s	297.600us	50	50	100.00
V2	back2back	aes_stress	10.000s	297.600us	50	50	100.00
		aes_b2b	24.000s	444.104us	50	50	100.00
V2	backpressure	aes_stress	10.000s	297.600us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	571.742us	50	50	100.00
		aes_config_error	13.000s	2.213ms	50	50	100.00
		aes_stress	10.000s	297.600us	50	50	100.00
		aes_alert_reset	25.000s	1.562ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	69.883us	50	50	100.00
		aes_config_error	13.000s	2.213ms	50	50	100.00
		aes_alert_reset	25.000s	1.562ms	50	50	100.00
V2	trigger_clear_test	aes_clear	11.000s	227.014us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	19.000s	1.588ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	25.000s	1.562ms	50	50	100.00
V2	stress	aes_stress	10.000s	297.600us	50	50	100.00
V2	sideload	aes_stress	10.000s	297.600us	50	50	100.00
		aes_sideload	11.000s	363.947us	50	50	100.00
V2	deinitialization	aes_deinit	25.000s	1.262ms	50	50	100.00
V2	stress_all	aes_stress_all	54.000s	2.636ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	72.569us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	111.173us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	111.173us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	74.602us	5	5	100.00
		aes_csr_rw	5.000s	96.341us	20	20	100.00
		aes_csr_aliasing	6.000s	129.793us	5	5	100.00
		aes_same_csr_outstanding	6.000s	354.794us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	74.602us	5	5	100.00
		aes_csr_rw	5.000s	96.341us	20	20	100.00
		aes_csr_aliasing	6.000s	129.793us	5	5	100.00
		aes_same_csr_outstanding	6.000s	354.794us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	1.063ms	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	502.170us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	502.170us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	502.170us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	502.170us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	96.834us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.465ms	5	5	100.00
		aes_tl_intg_err	8.000s	1.322ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	1.322ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	25.000s	1.562ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	502.170us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	571.742us	50	50	100.00
		aes_stress	10.000s	297.600us	50	50	100.00
		aes_alert_reset	25.000s	1.562ms	50	50	100.00
		aes_core_fi	21.000s	10.020ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	502.170us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	129.492us	50	50	100.00
		aes_stress	10.000s	297.600us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	297.600us	50	50	100.00
		aes_sideload	11.000s	363.947us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	129.492us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	129.492us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	129.492us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	129.492us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	129.492us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	297.600us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	297.600us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	562.886us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
		aes_ctr_fi	7.000s	280.835us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	562.886us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	42.000s	10.063ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	562.886us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_ctr_fi	7.000s	280.835us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
		aes_ctr_fi	7.000s	280.835us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	25.000s	1.562ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
		aes_ctr_fi	7.000s	280.835us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
		aes_ctr_fi	7.000s	280.835us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_ctr_fi	7.000s	280.835us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	562.886us	50	50	100.00
		aes_control_fi	40.000s	10.006ms	284	300	94.67
		aes_cipher_fi	42.000s	10.063ms	338	350	96.57
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	39.000s	19.352ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1561	1602	97.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	98.63	96.52	99.44	95.68	98.07	97.78	99.11	98.79

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 0.aes_cipher_fi.108971183466904772325301595514665161055052808765537539203515719256016388034167
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022213641 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022213641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.aes_cipher_fi.84590681128342554648163352143008387788893217153823063920734692528573714357583
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006530122 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006530122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 52.aes_control_fi.108215838684810343860868426466310282896519940673977862528801289353155054626308
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010171474 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010171474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 90.aes_control_fi.110943237729208149707491168640290334321285275240246409040568845078491687253351
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/90.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008036096 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008036096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
Job timed out after * minutes has 6 failures:
- Test aes_control_fi has 6 failures.
  - 93.aes_control_fi.111282038041912386408050831477329257981073151193381407240450667742781016730608
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/93.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 155.aes_control_fi.50104799742520466363696666369736368961464577381439223684886891459937112452810
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/155.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.89613398065057581635982563161377181506556282683222468905576523715263147366934
Line 237, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  99203674 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  99203674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.100832980014653298428262356835031116065268405906523344582246522191645531867331
Line 245, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2885458485 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2885458485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 12.aes_core_fi.73741226944376630361439562457315894787879756392545636238506732578777307132356
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019503169 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019503169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.aes_core_fi.64573401787137245057007842278747316898811569671822578918378798663878612396523
    Line 146, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025748905 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025748905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.96817744114532565311251233952866799664576213018344918792696297851825180276541
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  64954411 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  64954411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.76107550825982020932891381400675475264081108648804507501911417018089134078350
    Line 561, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 575163734 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 575163734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.20623497076898111202989292728147185280683237191435395105228630530429308434823
    Line 323, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 822210379 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 822210379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:908) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.111227475176383736866641639930263038972196648553637023433332932356556644275129
    Line 193, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1321764878 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1321764878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,865): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

25.aes_core_fi.112705795136273322702378923786636272485699303460082392139761125399989824693103
Line 130, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 7568564 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 7558147 PS)
  UVM_ERROR @   7568564 ps: (aes_cipher_core.sv:865) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @   7568564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---