AES/UNMASKED Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	178.097us	1	1	100.00
V1	smoke	aes_smoke	10.000s	122.700us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	84.758us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	80.641us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	4.255ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	903.684us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	89.251us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	80.641us	20	20	100.00
		aes_csr_aliasing	8.000s	903.684us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	122.700us	50	50	100.00
		aes_config_error	6.000s	222.278us	50	50	100.00
		aes_stress	6.000s	97.053us	50	50	100.00
V2	key_length	aes_smoke	10.000s	122.700us	50	50	100.00
		aes_config_error	6.000s	222.278us	50	50	100.00
		aes_stress	6.000s	97.053us	50	50	100.00
V2	back2back	aes_stress	6.000s	97.053us	50	50	100.00
		aes_b2b	9.000s	189.481us	50	50	100.00
V2	backpressure	aes_stress	6.000s	97.053us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	122.700us	50	50	100.00
		aes_config_error	6.000s	222.278us	50	50	100.00
		aes_stress	6.000s	97.053us	50	50	100.00
		aes_alert_reset	6.000s	489.648us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	68.476us	50	50	100.00
		aes_config_error	6.000s	222.278us	50	50	100.00
		aes_alert_reset	6.000s	489.648us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	227.135us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	203.867us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	489.648us	50	50	100.00
V2	stress	aes_stress	6.000s	97.053us	50	50	100.00
V2	sideload	aes_stress	6.000s	97.053us	50	50	100.00
		aes_sideload	7.000s	242.168us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	171.990us	50	50	100.00
V2	stress_all	aes_stress_all	19.000s	1.962ms	9	10	90.00
V2	alert_test	aes_alert_test	5.000s	69.983us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	155.175us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	155.175us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	84.758us	5	5	100.00
		aes_csr_rw	6.000s	80.641us	20	20	100.00
		aes_csr_aliasing	8.000s	903.684us	5	5	100.00
		aes_same_csr_outstanding	7.000s	101.275us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	84.758us	5	5	100.00
		aes_csr_rw	6.000s	80.641us	20	20	100.00
		aes_csr_aliasing	8.000s	903.684us	5	5	100.00
		aes_same_csr_outstanding	7.000s	101.275us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	6.000s	300.770us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	126.766us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	126.766us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	126.766us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	126.766us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	291.432us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	724.796us	5	5	100.00
		aes_tl_intg_err	8.000s	284.718us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	284.718us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	489.648us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	126.766us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	122.700us	50	50	100.00
		aes_stress	6.000s	97.053us	50	50	100.00
		aes_alert_reset	6.000s	489.648us	50	50	100.00
		aes_core_fi	23.000s	10.004ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	126.766us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	118.738us	50	50	100.00
		aes_stress	6.000s	97.053us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	97.053us	50	50	100.00
		aes_sideload	7.000s	242.168us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	118.738us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	118.738us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	118.738us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	118.738us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	118.738us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	97.053us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	97.053us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	104.588us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
		aes_ctr_fi	6.000s	155.250us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	104.588us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.004ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	104.588us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_ctr_fi	6.000s	155.250us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
		aes_ctr_fi	6.000s	155.250us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	489.648us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
		aes_ctr_fi	6.000s	155.250us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
		aes_ctr_fi	6.000s	155.250us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_ctr_fi	6.000s	155.250us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	104.588us	50	50	100.00
		aes_control_fi	28.000s	10.005ms	280	300	93.33
		aes_cipher_fi	32.000s	10.004ms	329	350	94.00
V2S		TOTAL			943	985	95.74
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	15.000s	1.478ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1549	1602	96.69

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.30	97.64	94.68	98.80	93.60	98.07	91.11	98.85	97.99

Failure Buckets

Job timed out after * minutes has 23 failures:
- Test aes_control_fi has 13 failures.
  - 19.aes_control_fi.25579781654092422267722288453671105631623960101303849990328556536717297660639
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 22.aes_control_fi.64408072897825104440614715026969803287979797793046724535889308106970532981024
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 10 failures.
  - 91.aes_cipher_fi.45444361248375623558729413532512073805681689815647013026280433432760240064779
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/91.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 137.aes_cipher_fi.33370651897839667853033156096614432900520784390613813625941093270654549712308
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/137.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 75.aes_cipher_fi.69972679421846437736460353226901247131833882895837862435791588755335930002181
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025133106 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025133106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 154.aes_cipher_fi.71289291687085640139763987366586040735050717377407499960444660959294213557078
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/154.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004135655 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004135655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 9.aes_control_fi.87053985787248106571704043333263784620843927670525335664542176063683697559624
    Line 129, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004994136 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004994136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 86.aes_control_fi.47972686422756388824785849352820613595134575482088783310613326590855762702833
    Line 130, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/86.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10058301418 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10058301418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.91831643575212323688372469541973914469749194195497043313541934013792739084587
    Line 734, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1478423854 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1478423854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.113027148194615633083498316233398729064740109904675680067242672382396588856283
    Line 256, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 233252399 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 233252399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 3 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.99705479237972488454065515069588849800142415060918305529461836255090533776507
Line 322, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 90511916 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 90501499 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 90511916 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 90501499 PS)
  UVM_ERROR @  90511916 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

2.aes_stress_all_with_rand_reset.92588938246000648521822077957827013997183723717984547627426767631635035504393
Line 446, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 470912661 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 470870994 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 470912661 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 470870994 PS)
  UVM_ERROR @ 470912661 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Test aes_stress_all has 1 failures.

9.aes_stress_all.54718393516599274137130858599026599134611663756331483500919576804172927271727
Line 4582, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 353182966 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 353016299 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 353182966 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 353016299 PS)
  UVM_ERROR @ 353182966 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.86482687475398300234810621955827869889214770583048660227822054157536194556285
Line 930, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1296431758 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1296431758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.68946074788888782127486703875722705284340558659747079806076612808071596704458
Line 921, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 277699899 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 277699899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.58037313571000172044222313207579507106790384006225019611402282250749678726293
    Line 156, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  53241015 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  53241015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.67567979667240857285352379315692371874520170591071504058241494798858598708732
    Line 162, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  91356172 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  91356172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 59.aes_core_fi.111693596208496239204001448088804576491816225317195639958712959834501516136719
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004150099 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004150099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```