CSRNG Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	296.079us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	119.112us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	174.658us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	2.196ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	90.945us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	105.613us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	174.658us	20	20	100.00
		csrng_csr_aliasing	7.000s	90.945us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	997.420us	200	200	100.00
V2	alerts	csrng_alert	51.000s	3.468ms	500	500	100.00
V2	err	csrng_err	6.000s	93.183us	499	500	99.80
V2	cmds	csrng_cmds	8.517m	53.557ms	50	50	100.00
V2	life cycle	csrng_cmds	8.517m	53.557ms	50	50	100.00
V2	stress_all	csrng_stress_all	15.417m	50.503ms	49	50	98.00
V2	intr_test	csrng_intr_test	6.000s	79.234us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	111.263us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	22.000s	1.577ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	22.000s	1.577ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	119.112us	5	5	100.00
		csrng_csr_rw	6.000s	174.658us	20	20	100.00
		csrng_csr_aliasing	7.000s	90.945us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	377.199us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	119.112us	5	5	100.00
		csrng_csr_rw	6.000s	174.658us	20	20	100.00
		csrng_csr_aliasing	7.000s	90.945us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	377.199us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	7.000s	79.714us	5	5	100.00
		csrng_tl_intg_err	14.000s	753.364us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	84.581us	50	50	100.00
		csrng_csr_rw	6.000s	174.658us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	51.000s	3.468ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	15.417m	50.503ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	51.000s	3.468ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	15.417m	50.503ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	51.000s	3.468ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	753.364us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
		csrng_sec_cm	7.000s	79.714us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	997.420us	200	200	100.00
		csrng_err	6.000s	93.183us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.883m	4.705ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.79	98.63	96.69	99.97	97.36	92.15	100.00	97.36	90.93

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:

  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.17963876872128092401781483890783082845636628683120506364489386537677904640035
      Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 447103483 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 447103483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.12694461626413853383506617438738687846174761617841479727174340680099133689389
      Line 117, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3072970918 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3072970918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 46.csrng_stress_all.60481762471503562720018527177726172321171002809800161144002838084349025714010
      Line 151, in log /nightly/runs/scratch/master/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log

        UVM_ERROR @ 4197766976 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 4197766976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:

  • Test csrng_err has 1 failures.

    • 497.csrng_err.9440504326113168344815874576988275849372085056105658055127482748724323000812
      Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/497.csrng_err/latest/run.log

        UVM_ERROR @   4967895 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
        UVM_INFO @   4967895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---