DMA Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	48.000s	3.349ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	49.000s	797.369us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	47.000s	5.553ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	38.795us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	36.116us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	17.000s	485.764us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	11.000s	2.228ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	30.473us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	36.116us	20	20	100.00
		dma_csr_aliasing	11.000s	2.228ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.667m	3.642ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	11.400m	203.006ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	5.400m	49.304ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	33.883m	295.972ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	11.400m	203.006ms	3	3	100.00
V2	dma_abort	dma_abort	46.000s	496.315us	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.467m	15.312ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	43.161us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	126.005us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	126.005us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	38.795us	5	5	100.00
		dma_csr_rw	5.000s	36.116us	20	20	100.00
		dma_csr_aliasing	11.000s	2.228ms	5	5	100.00
		dma_same_csr_outstanding	5.000s	164.308us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	38.795us	5	5	100.00
		dma_csr_rw	5.000s	36.116us	20	20	100.00
		dma_csr_aliasing	11.000s	2.228ms	5	5	100.00
		dma_same_csr_outstanding	5.000s	164.308us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	1.033m	283.346us	5	5	100.00
		dma_generic_stress	33.883m	295.972ms	5	5	100.00
		dma_handshake_stress	11.400m	203.006ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	725.739us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.317m	10.491ms	5	5	100.00
		dma_longer_transfer	50.000s	1.762ms	5	5	100.00
		TOTAL			304	304	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
76.38	96.98	95.20	96.94	96.35	82.72	82.76	97.77	42.37