EDN Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.480s 19.193us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.860s 19.785us 5 5 100.00
V1 csr_rw edn_csr_rw 1.820s 36.908us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.560s 584.534us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.170s 146.557us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.220s 41.677us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.820s 36.908us 20 20 100.00
edn_csr_aliasing 2.170s 146.557us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.710m 12.936ms 300 300 100.00
V2 csrng_commands edn_genbits 1.710m 12.936ms 300 300 100.00
V2 genbits edn_genbits 1.710m 12.936ms 300 300 100.00
V2 interrupts edn_intr 2.670s 22.732us 50 50 100.00
V2 alerts edn_alert 2.690s 25.864us 200 200 100.00
V2 errs edn_err 2.830s 32.818us 100 100 100.00
V2 disable edn_disable 2.400s 16.004us 50 50 100.00
edn_disable_auto_req_mode 3.120s 26.217us 50 50 100.00
V2 stress_all edn_stress_all 8.850s 369.468us 50 50 100.00
V2 intr_test edn_intr_test 1.820s 24.989us 50 50 100.00
V2 alert_test edn_alert_test 2.700s 56.554us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.340s 345.334us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.340s 345.334us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.860s 19.785us 5 5 100.00
edn_csr_rw 1.820s 36.908us 20 20 100.00
edn_csr_aliasing 2.170s 146.557us 5 5 100.00
edn_same_csr_outstanding 2.020s 32.605us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.860s 19.785us 5 5 100.00
edn_csr_rw 1.820s 36.908us 20 20 100.00
edn_csr_aliasing 2.170s 146.557us 5 5 100.00
edn_same_csr_outstanding 2.020s 32.605us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.520s 951.359us 5 5 100.00
edn_tl_intg_err 3.040s 107.371us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.110s 56.858us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.690s 25.864us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.520s 951.359us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.520s 951.359us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.520s 951.359us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.520s 951.359us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.690s 25.864us 200 200 100.00
edn_sec_cm 7.520s 951.359us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.690s 25.864us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.040s 107.371us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.791m 20.561ms 26 50 52.00
V3 TOTAL 26 50 52.00
TOTAL 1106 1130 97.88

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.96 98.32 94.29 97.02 93.02 96.36 99.78 92.94

Failure Buckets