HMAC Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	17.250s	2.944ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.440s	14.295us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.640s	58.012us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.450s	3.207ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.940s	448.573us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.498m	176.462ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.640s	58.012us	20	20	100.00
		hmac_csr_aliasing	8.940s	448.573us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.538m	6.167ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.616m	1.553ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.628m	27.148ms	30	30	100.00
		hmac_test_sha384_vectors	9.756m	16.757ms	75	75	100.00
		hmac_test_sha512_vectors	8.391m	13.456ms	75	75	100.00
		hmac_test_hmac256_vectors	16.530s	348.897us	50	50	100.00
		hmac_test_hmac384_vectors	17.790s	421.926us	60	60	100.00
		hmac_test_hmac512_vectors	18.890s	2.269ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	41.050s	3.074ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	21.441m	15.693ms	10	10	100.00
V2	error	hmac_error	1.401m	7.633ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.886m	9.506ms	10	10	100.00
V2	save_and_restore	hmac_smoke	17.250s	2.944ms	10	10	100.00
		hmac_long_msg	1.538m	6.167ms	10	10	100.00
		hmac_back_pressure	1.616m	1.553ms	25	25	100.00
		hmac_datapath_stress	21.441m	15.693ms	10	10	100.00
		hmac_burst_wr	41.050s	3.074ms	50	50	100.00
		hmac_stress_all	24.993m	9.980ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	17.250s	2.944ms	10	10	100.00
		hmac_long_msg	1.538m	6.167ms	10	10	100.00
		hmac_back_pressure	1.616m	1.553ms	25	25	100.00
		hmac_datapath_stress	21.441m	15.693ms	10	10	100.00
		hmac_wipe_secret	1.886m	9.506ms	10	10	100.00
		hmac_test_sha256_vectors	4.628m	27.148ms	30	30	100.00
		hmac_test_sha384_vectors	9.756m	16.757ms	75	75	100.00
		hmac_test_sha512_vectors	8.391m	13.456ms	75	75	100.00
		hmac_test_hmac256_vectors	16.530s	348.897us	50	50	100.00
		hmac_test_hmac384_vectors	17.790s	421.926us	60	60	100.00
		hmac_test_hmac512_vectors	18.890s	2.269ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	17.250s	2.944ms	10	10	100.00
		hmac_long_msg	1.538m	6.167ms	10	10	100.00
		hmac_back_pressure	1.616m	1.553ms	25	25	100.00
		hmac_datapath_stress	21.441m	15.693ms	10	10	100.00
		hmac_burst_wr	41.050s	3.074ms	50	50	100.00
		hmac_error	1.401m	7.633ms	10	10	100.00
		hmac_wipe_secret	1.886m	9.506ms	10	10	100.00
		hmac_test_sha256_vectors	4.628m	27.148ms	30	30	100.00
		hmac_test_sha384_vectors	9.756m	16.757ms	75	75	100.00
		hmac_test_sha512_vectors	8.391m	13.456ms	75	75	100.00
		hmac_test_hmac256_vectors	16.530s	348.897us	50	50	100.00
		hmac_test_hmac384_vectors	17.790s	421.926us	60	60	100.00
		hmac_test_hmac512_vectors	18.890s	2.269ms	75	75	100.00
		hmac_stress_all	24.993m	9.980ms	50	50	100.00
V2	stress_all	hmac_stress_all	24.993m	9.980ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.140s	42.569us	50	50	100.00
V2	intr_test	hmac_intr_test	2.360s	14.849us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.500s	392.866us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.500s	392.866us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.440s	14.295us	5	5	100.00
		hmac_csr_rw	2.640s	58.012us	20	20	100.00
		hmac_csr_aliasing	8.940s	448.573us	5	5	100.00
		hmac_same_csr_outstanding	3.740s	326.719us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.440s	14.295us	5	5	100.00
		hmac_csr_rw	2.640s	58.012us	20	20	100.00
		hmac_csr_aliasing	8.940s	448.573us	5	5	100.00
		hmac_same_csr_outstanding	3.740s	326.719us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.590s	113.170us	5	5	100.00
		hmac_tl_intg_err	5.800s	1.126ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.800s	1.126ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	17.250s	2.944ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.710s	126.844us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	5.424m	9.197ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	4.200s	295.426us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.06	100.00	97.14	100.00	100.00	100.00	100.00	47.30