I2C Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.400m	15.072ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	37.520s	1.668ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.780s	22.883us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.220s	48.298us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.920s	4.340ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.560s	272.385us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.510s	31.771us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.220s	48.298us	20	20	100.00
		i2c_csr_aliasing	2.560s	272.385us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	15.800s	3.027ms	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	35.082m	23.485ms	16	50	32.00
V2	host_maxperf	i2c_host_perf	30.046m	47.927ms	50	50	100.00
V2	host_override	i2c_host_override	2.340s	26.531us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.077m	5.316ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.026m	19.548ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.670s	599.101us	50	50	100.00
		i2c_host_fifo_fmt_empty	29.940s	1.012ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.370s	220.168us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.500m	13.926ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	34.410s	1.069ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.060s	175.494us	18	50	36.00
V2	target_glitch	i2c_target_glitch	14.640s	4.181ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	6.663m	26.317ms	47	50	94.00
V2	target_maxperf	i2c_target_perf	9.390s	8.740ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.033m	1.459ms	50	50	100.00
		i2c_target_intr_smoke	12.100s	1.524ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.090s	959.048us	50	50	100.00
		i2c_target_fifo_reset_tx	3.370s	276.244us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	11.361m	54.078ms	50	50	100.00
		i2c_target_stress_rd	1.033m	1.459ms	50	50	100.00
		i2c_target_intr_stress_wr	3.837m	21.607ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	10.390s	5.105ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.145m	5.399ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	8.230s	1.367ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	43.880s	10.199ms	26	50	52.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.290s	1.112ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.420s	649.842us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	30.046m	47.927ms	50	50	100.00
		i2c_host_perf_precise	9.092m	23.143ms	49	50	98.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	34.410s	1.069ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	27.550s	2.052ms	47	50	94.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.210s	2.323ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.070s	640.017us	50	50	100.00
		i2c_target_nack_txstretch	3.300s	631.620us	31	50	62.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	22.690s	712.140us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.510s	513.273us	50	50	100.00
V2	alert_test	i2c_alert_test	2.240s	201.573us	50	50	100.00
V2	intr_test	i2c_intr_test	2.190s	25.649us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.060s	468.796us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.060s	468.796us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.780s	22.883us	5	5	100.00
		i2c_csr_rw	2.220s	48.298us	20	20	100.00
		i2c_csr_aliasing	2.560s	272.385us	5	5	100.00
		i2c_same_csr_outstanding	2.320s	143.137us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.780s	22.883us	5	5	100.00
		i2c_csr_rw	2.220s	48.298us	20	20	100.00
		i2c_csr_aliasing	2.560s	272.385us	5	5	100.00
		i2c_same_csr_outstanding	2.320s	143.137us	20	20	100.00
V2		TOTAL			1672	1792	93.30
V2S	tl_intg_err	i2c_tl_intg_err	3.070s	126.058us	20	20	100.00
		i2c_sec_cm	2.620s	266.772us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.070s	126.058us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	22.960s	4.009ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.780s	1.480ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	40.000s	1.464ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1852	2042	90.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.00	97.32	89.67	74.17	72.02	94.27	98.52	90.06

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 46 failures:

Test i2c_host_stress_all has 27 failures.

0.i2c_host_stress_all.15471121870604269568106573169435878663325382666610789949740348109478341897059
Line 128, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 71399917174 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3118418

1.i2c_host_stress_all.11921927007577124401329432354310754077250523201553730679049885492496508897637
Line 159, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 82083827265 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7035858

... and 25 more failures.

Test i2c_host_mode_toggle has 19 failures.

4.i2c_host_mode_toggle.3306193440397021043824396956972989654145147772427193477175138920716033753851
Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 482186006 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10583

9.i2c_host_mode_toggle.65217482559806963575123223981570604624859078201704408152029415219255339453642
Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 177064470 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @14861

... and 17 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
- Test i2c_target_hrst has 24 failures.
  - 1.i2c_target_hrst.110876353563057210043881696016680735640920268431547907182287617562522314704079
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 11674129586 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 11674129586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.53661324669498429375527661643422751107911742937549140142614658012124573782466
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10458631352 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10458631352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 23 failures:
- Test i2c_target_unexp_stop has 23 failures.
  - 1.i2c_target_unexp_stop.105596545729597087319903503101899628633065668740276500715611435760342390404848
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 265411232 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 119 [0x77])
  UVM_INFO @ 265411232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.29570116921554437295096562949899827294675085525104570354582661077912598817407
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 249955668 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 71 [0x47])
  UVM_INFO @ 249955668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 19 failures:
- Test i2c_target_nack_txstretch has 19 failures.
  - 2.i2c_target_nack_txstretch.41907214007638664024652932827087128537209809349452830171830491491424288151927
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 209550287 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 209550287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_nack_txstretch.43734274869810521293060146492699171925341273029336598237129509703832609899197
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 3899527439 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 3899527439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

0.i2c_host_stress_all_with_rand_reset.102135331856116816297153158657435033680078389726745885403801733146771667928060
Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1772229843 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1772229843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_host_stress_all_with_rand_reset.66758914685566149486155393444471198530457417632940856432913590878719486766340
Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1664931892 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1664931892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 9 failures.

0.i2c_target_stress_all_with_rand_reset.13022006817223367480791602866155180834532990932996289099957332703848297037614
Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2236418253 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2236418253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.97555244027570147466370072302206885376315804026056517076312471062262986377881
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1041996387 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1041996387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 4.i2c_target_unexp_stop.59574157603308873141879626863078684702897339144935867787486479566065283715811
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 232266369 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 232266369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_unexp_stop.35469766481677719944374860275026628011954972705082606880153899772631131364397
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 503692291 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 503692291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 12 failures.

1.i2c_host_mode_toggle.96716595945230073252467644801555105615554012781545895649196010269449807027105
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 383721516 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

2.i2c_host_mode_toggle.114570456460029399879220968431516537523616178290476531867077219326804999701211
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 152228673 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

Test i2c_host_perf_precise has 1 failures.

7.i2c_host_perf_precise.83637578853126699826632186239602973449624230559065701638186432094075550029527
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_perf_precise/latest/run.log

  UVM_ERROR @ 3050889790 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 10 failures:

Test i2c_target_unexp_stop has 10 failures.

0.i2c_target_unexp_stop.62440232798248294747187817641295938608962272243792424947430036723106159157220
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 941513213 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 941513213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.i2c_target_unexp_stop.69215582178937440879527218322404781951217198903635345404550078593444763996794
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  96689844 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  96689844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:

Test i2c_host_stress_all has 4 failures.

11.i2c_host_stress_all.7128312636521059636939419431280860876770111185403861174362436187917670264
Line 237, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 87175854777 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6733184

28.i2c_host_stress_all.38646292954237882098481286072213638639094167404920889884455373377543148922316
Line 192, in log /nightly/runs/scratch/master/i2c-sim-vcs/28.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 10505359657 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2957880

... and 2 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 16.i2c_target_stretch.81512219415492168741771387633833238581836567816746863784222367430178011818113
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001547751 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001547751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 37.i2c_target_stretch.15952145947042997260530500385942485631210593903895102760035912101196402253196
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/37.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10059024192 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10059024192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Job timed out after * minutes has 3 failures:
- Test i2c_host_stress_all has 3 failures.
  - 5.i2c_host_stress_all.6320489671997558212036125068134844722207211919685072304270264303918843264266
    Log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 9.i2c_host_stress_all.93368739353517485356561979135955739889207422169161148080376440052146728891499
    Log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
- Test i2c_target_stress_all has 3 failures.
  - 10.i2c_target_stress_all.53056372859503553082045715075245527931748910941918568341054491043373109419660
    Line 117, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 80848636717 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 80848636717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.i2c_target_stress_all.58345172012436497178934198099281936857115186415961860043216265104070625094452
    Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 96934010913 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 96934010913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_tx_stretch_ctrl has 3 failures.
  - 20.i2c_target_tx_stretch_ctrl.91298049958136321353183426361861290877841730730889538803731552955913235224354
    Line 129, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 29.i2c_target_tx_stretch_ctrl.4502738947620360672629820497669913330777526454754143458980283366501709166217
    Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_host_stress_all_with_rand_reset.39202892467679753509993406373728781219918045485675847442195744755883564189202
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3319033065 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
  UVM_INFO @ 3319033065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:811) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_target_stress_all_with_rand_reset.52607747909431820853358867379592462080440880699869012695646697469134516272074
    Line 112, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1463591864 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1463591864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 31.i2c_host_mode_toggle.17737231709323802659261271739986286397196700412825675342675573102857779228135
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/31.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  30347496 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xa59d9a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  30347496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```