KEYMGR Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	31.610s	6.037ms	50	50	100.00
V1	random	keymgr_random	41.890s	2.177ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.680s	241.018us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.330s	79.669us	14	20	70.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.560s	265.942us	2	5	40.00
V1	csr_aliasing	keymgr_csr_aliasing	6.360s	130.414us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.020s	33.606us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.330s	79.669us	14	20	70.00
		keymgr_csr_aliasing	6.360s	130.414us	5	5	100.00
V1		TOTAL			145	155	93.55
V2	cfgen_during_op	keymgr_cfg_regwen	1.319m	18.539ms	50	50	100.00
V2	sideload	keymgr_sideload	31.150s	14.409ms	50	50	100.00
		keymgr_sideload_kmac	25.730s	6.286ms	50	50	100.00
		keymgr_sideload_aes	29.730s	1.521ms	50	50	100.00
		keymgr_sideload_otbn	33.500s	5.129ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	12.010s	815.699us	49	50	98.00
V2	lc_disable	keymgr_lc_disable	5.020s	736.396us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.710s	239.682us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	32.190s	1.984ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	9.540s	6.041ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	8.520s	1.278ms	48	50	96.00
V2	stress_all	keymgr_stress_all	5.097m	27.108ms	50	50	100.00
V2	intr_test	keymgr_intr_test	2.280s	18.443us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.030s	26.808us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.950s	147.321us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.950s	147.321us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.680s	241.018us	5	5	100.00
		keymgr_csr_rw	2.330s	79.669us	14	20	70.00
		keymgr_csr_aliasing	6.360s	130.414us	5	5	100.00
		keymgr_same_csr_outstanding	3.530s	85.153us	19	20	95.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.680s	241.018us	5	5	100.00
		keymgr_csr_rw	2.330s	79.669us	14	20	70.00
		keymgr_csr_aliasing	6.360s	130.414us	5	5	100.00
		keymgr_same_csr_outstanding	3.530s	85.153us	19	20	95.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
		keymgr_tl_intg_err	6.910s	818.662us	11	20	55.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.270s	835.926us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.270s	835.926us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.270s	835.926us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.270s	835.926us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.060s	476.881us	12	20	60.00
V2S	prim_count_check	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	6.910s	818.662us	11	20	55.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.270s	835.926us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.319m	18.539ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	41.890s	2.177ms	50	50	100.00
		keymgr_csr_rw	2.330s	79.669us	14	20	70.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	41.890s	2.177ms	50	50	100.00
		keymgr_csr_rw	2.330s	79.669us	14	20	70.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	41.890s	2.177ms	50	50	100.00
		keymgr_csr_rw	2.330s	79.669us	14	20	70.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.020s	736.396us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	9.540s	6.041ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	9.540s	6.041ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	41.890s	2.177ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	8.980s	659.726us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	18.270s	4.135ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.020s	736.396us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	18.270s	4.135ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	18.270s	4.135ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	18.270s	4.135ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.940s	1.453ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	18.270s	4.135ms	50	50	100.00
V2S		TOTAL			148	165	89.70
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	21.160s	768.011us	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1063	1110	95.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.10	97.95	98.58	100.00	99.02	98.63	91.26

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 28 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 8 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.93644636065189501121827567205196893492078342976023669064278850255686839628347
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @   9038722 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @   9038722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_shadow_reg_errors_with_csr_rw.98749732949620154558937696261130143752765938971701583533595941526939756742895
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  35680822 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  35680822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test keymgr_csr_bit_bash has 3 failures.

0.keymgr_csr_bit_bash.16317687351610053957884798030311529622906002379117246491531775937118379996968
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 3269142405 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 3269142405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_csr_bit_bash.16831914786725802725312655615606913080657149370845168308960539755384486413297
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @ 1427083664 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @ 1427083664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_same_csr_outstanding has 1 failures.

0.keymgr_same_csr_outstanding.44002974606207857089916228882550561611101066371396940239294880208611160456410
Line 80, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  56336177 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  56336177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_tl_intg_err has 9 failures.

1.keymgr_tl_intg_err.90724611429358041461261740145711596266398523486131598504915693447140764253603
Line 168, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 218560155 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 218560155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_tl_intg_err.20489888113972605928774151592962656101456268027345916250887993631741813534651
Line 91, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  15528472 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  15528472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test keymgr_csr_rw has 6 failures.

3.keymgr_csr_rw.94523239764524613900575956667090492094646224035935087992540635610203102480215
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  11796530 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  11796530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_csr_rw.7244723818612869592137349697350130815982911580920440767296408828585471378796
Line 81, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @   9921725 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @   9921725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test keymgr_stress_all_with_rand_reset has 13 failures.
  - 0.keymgr_stress_all_with_rand_reset.921272931197694043006588656892806888792739874202330719191425326436652731609
    Line 189, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 105320951 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105320951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.94285335806987853697253573882523169809253525963286612030818263954709642277890
    Line 238, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127028687 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 127028687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_ERROR (cip_base_scoreboard.sv:333) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 11.keymgr_hwsw_invalid_input.23454555274977437856622216099411308980766967674255386551473184702973362136376
    Line 466, in log /nightly/runs/scratch/master/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  50234173 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  50234173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_direct_to_disabled has 1 failures.
  - 43.keymgr_direct_to_disabled.36848595094291813472701635598364462302648133353103854613709149400679718018437
    Line 212, in log /nightly/runs/scratch/master/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest/run.log
```
  UVM_ERROR @  14421967 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  14421967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 48.keymgr_sync_async_fault_cross.98038684436927137039707395173068642180455465036955257244637483913194047281507
    Line 134, in log /nightly/runs/scratch/master/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  25116968 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  25116968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:283) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 0.keymgr_sync_async_fault_cross.61280742913019629409598774389413246692599960593992108374291799011869442179205
    Line 139, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  33776257 ps: (cip_base_scoreboard.sv:283) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  33776257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 19.keymgr_lc_disable.40939443287431989679968573935559528092897171996574037998858612280400037682069
    Line 270, in log /nightly/runs/scratch/master/keymgr-sim-vcs/19.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 191354204 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7
  UVM_INFO @ 191354204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

49.keymgr_lc_disable.23028539669588499892022718140056796502873025075546045540744545309055330251317
Line 211, in log /nightly/runs/scratch/master/keymgr-sim-vcs/49.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 171037150 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3657553565979331374459308257377802878910341434135515643180947070915868031598439747553970378098559744967692635812847007497128144466796218100610373780872594 [0x45d5bfda448ffca049afe9fcd88e2ebd8a350e78dd348c72baabfb9ff36de1fb1d5cd6c77a767e1ac5a39e2bcd46872ef86fea704249746157d3d2226c959d92] vs 3657553565979331374459308257377802878910341434135515643180947070915868031598439747553970378098559744967692635812847007497128144466796218100610373780872594 [0x45d5bfda448ffca049afe9fcd88e2ebd8a350e78dd348c72baabfb9ff36de1fb1d5cd6c77a767e1ac5a39e2bcd46872ef86fea704249746157d3d2226c959d92]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @ 171037150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---