KEYMGR_DPE Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	2.581m	27.267ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.190s	99.312us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.100s	490.578us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	9.400s	900.492us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	7.990s	570.250us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.940s	87.852us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.100s	490.578us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.990s	570.250us	5	5	100.00
V1		TOTAL			102	105	97.14
V2	intr_test	keymgr_dpe_intr_test	2.110s	11.118us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.170s	228.563us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.410s	519.057us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.410s	519.057us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.190s	99.312us	5	5	100.00
		keymgr_dpe_csr_rw	2.100s	490.578us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.990s	570.250us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.430s	90.596us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.190s	99.312us	5	5	100.00
		keymgr_dpe_csr_rw	2.100s	490.578us	20	20	100.00
		keymgr_dpe_csr_aliasing	7.990s	570.250us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.430s	90.596us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	11.110s	5.958ms	5	5	100.00
		keymgr_dpe_tl_intg_err	6.550s	226.798us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.800s	135.068us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.800s	135.068us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.800s	135.068us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.800s	135.068us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.100s	525.612us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	11.110s	5.958ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	11.110s	5.958ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			307	310	99.03

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.06	97.57	90.70	63.14	76.92	94.91	98.57	17.60

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:
- Test keymgr_dpe_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.keymgr_dpe_csr_mem_rw_with_rand_reset.97833913073519343999447788450590845817361462141167207138913669960936043878114
    Line 96, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/3.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  27288094 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
  UVM_INFO @  27288094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_dpe_smoke has 1 failures.
  - 6.keymgr_dpe_smoke.37882410173541255334738577564864715391730875543253062202185905835937000574628
    Line 1684, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/6.keymgr_dpe_smoke/latest/run.log
```
  UVM_ERROR @ 688937277 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @ 688937277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:

Test keymgr_dpe_smoke has 1 failures.

44.keymgr_dpe_smoke.41405629358655315178437638198294157320495976581337344482696544510929345730582
Line 2570, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/44.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 375437755 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h8483561eea5fce7ab51299d7a7869fea5c58d86050c51af0f0857994cb0d158cb63edfdaf127698fb12a141db6162eef1e36c2d466e1aedc9d0e47872d2f8909 vs. act 'h0
  UVM_INFO @ 375437755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---