KMAC/MASKED Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.291m	6.354ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.970s	54.525us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.370s	66.534us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.960s	1.515ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.330s	9.634ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.030s	151.970us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.370s	66.534us	20	20	100.00
		kmac_csr_aliasing	8.330s	9.634ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.030s	93.880us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.180s	161.217us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.571m	151.483ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.996m	437.335ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.461m	329.779ms	5	5	100.00
		kmac_test_vectors_sha3_256	28.614m	121.706ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.390m	70.616ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.744m	192.415ms	5	5	100.00
		kmac_test_vectors_shake_128	38.198m	109.295ms	5	5	100.00
		kmac_test_vectors_shake_256	30.410m	177.665ms	5	5	100.00
		kmac_test_vectors_kmac	3.950s	252.447us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.370s	306.999us	5	5	100.00
V2	sideload	kmac_sideload	6.971m	21.782ms	50	50	100.00
V2	app	kmac_app	6.173m	15.758ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.144m	104.725ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.566m	97.690ms	50	50	100.00
V2	error	kmac_error	6.980m	20.809ms	50	50	100.00
V2	key_error	kmac_key_error	22.250s	20.931ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.220s	679.915us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.600s	26.443ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.200s	793.654us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.318m	32.707ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.390s	3.954ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.996m	308.238ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.040s	37.063us	50	50	100.00
V2	alert_test	kmac_alert_test	2.340s	151.021us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.130s	129.987us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.130s	129.987us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.970s	54.525us	5	5	100.00
		kmac_csr_rw	2.370s	66.534us	20	20	100.00
		kmac_csr_aliasing	8.330s	9.634ms	5	5	100.00
		kmac_same_csr_outstanding	3.140s	138.897us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.970s	54.525us	5	5	100.00
		kmac_csr_rw	2.370s	66.534us	20	20	100.00
		kmac_csr_aliasing	8.330s	9.634ms	5	5	100.00
		kmac_same_csr_outstanding	3.140s	138.897us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.930s	260.967us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.930s	260.967us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.930s	260.967us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.930s	260.967us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.240s	229.851us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	1.509m	8.513ms	5	5	100.00
		kmac_tl_intg_err	4.660s	358.728us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.660s	358.728us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.390s	3.954ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.291m	6.354ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.971m	21.782ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.930s	260.967us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.509m	8.513ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.509m	8.513ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.509m	8.513ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.291m	6.354ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.390s	3.954ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.509m	8.513ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.233m	16.293ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.291m	6.354ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.705m	1.817ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			923	940	98.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.39	99.09	94.47	99.89	80.28	97.05	99.06	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

2.kmac_shadow_reg_errors_with_csr_rw.63287371716983325504259560555463075234608737585876075514791473149875752814893
Line 81, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  78817791 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  78817791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors_with_csr_rw.26457146277845842645148780080423748785400247047781261081343882303906524138272
Line 81, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  14132085 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  14132085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_tl_intg_err has 4 failures.

2.kmac_tl_intg_err.102115236000808932212596834744285509437169797299647505217295631442378111907550
Line 87, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  44130179 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  44130179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_tl_intg_err.28522613655016166477848363025078348694148481600184672959193010848051120914332
Line 99, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  30649289 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  30649289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.42638704046650674895115682756677069084020881770705734665418962455620207917131
    Line 98, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 462590496 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 462590496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.55240046754851924484798788041720019142762277107545105230244929979823196537536
    Line 136, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4182176831 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 4182176831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.