KMAC/UNMASKED Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.328m	46.788ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.400s	46.498us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.330s	74.099us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.290s	4.300ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.060s	1.575ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.160s	138.225us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.330s	74.099us	20	20	100.00
		kmac_csr_aliasing	8.060s	1.575ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.140s	35.296us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.920s	37.727us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.787m	132.539ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.671m	51.196ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	22.419m	331.107ms	5	5	100.00
		kmac_test_vectors_sha3_256	27.022m	157.100ms	5	5	100.00
		kmac_test_vectors_sha3_384	16.951m	227.339ms	5	5	100.00
		kmac_test_vectors_sha3_512	13.700m	105.934ms	5	5	100.00
		kmac_test_vectors_shake_128	37.404m	444.656ms	5	5	100.00
		kmac_test_vectors_shake_256	28.509m	182.155ms	5	5	100.00
		kmac_test_vectors_kmac	3.320s	90.096us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.470s	990.005us	5	5	100.00
V2	sideload	kmac_sideload	5.669m	25.582ms	50	50	100.00
V2	app	kmac_app	4.575m	232.455ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.662m	14.235ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.328m	21.659ms	50	50	100.00
V2	error	kmac_error	5.567m	13.317ms	50	50	100.00
V2	key_error	kmac_key_error	12.900s	7.345ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.151m	10.084ms	32	50	64.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.780s	1.232ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	53.220s	2.726ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.422m	51.572ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.530s	5.545ms	50	50	100.00
V2	stress_all	kmac_stress_all	31.122m	200.527ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.160s	14.654us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	24.420us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.550s	581.153us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.550s	581.153us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.400s	46.498us	5	5	100.00
		kmac_csr_rw	2.330s	74.099us	20	20	100.00
		kmac_csr_aliasing	8.060s	1.575ms	5	5	100.00
		kmac_same_csr_outstanding	3.290s	323.310us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.400s	46.498us	5	5	100.00
		kmac_csr_rw	2.330s	74.099us	20	20	100.00
		kmac_csr_aliasing	8.060s	1.575ms	5	5	100.00
		kmac_same_csr_outstanding	3.290s	323.310us	20	20	100.00
V2		TOTAL			722	740	97.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.910s	391.784us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.910s	391.784us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.910s	391.784us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.910s	391.784us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.130s	362.634us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	53.440s	9.194ms	5	5	100.00
		kmac_tl_intg_err	4.520s	201.193us	14	20	70.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.520s	201.193us	14	20	70.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.530s	5.545ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.328m	46.788ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.669m	25.582ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.910s	391.784us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.440s	9.194ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.440s	9.194ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.440s	9.194ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.328m	46.788ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.530s	5.545ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.440s	9.194ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.148m	64.304ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.328m	46.788ms	50	50	100.00
V2S		TOTAL			62	75	82.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.202m	17.263ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			903	940	96.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.87	97.18	94.42	100.00	74.38	95.93	99.02	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 13 failures:

Test kmac_tl_intg_err has 6 failures.

3.kmac_tl_intg_err.98040203755111709021163074554909844150952367627164423094095341397048114186154
Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  49246147 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  49246147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_tl_intg_err.54028635286267516481568229119688628294425896400435226425395624638654045039130
Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @   8360162 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @   8360162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

5.kmac_shadow_reg_errors_with_csr_rw.70540385469967013192352987949906563735043046978044394409351855813501458984778
Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  33298558 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  33298558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.28330563999867711647904468565552981317296721567553101734625933972986986298561
Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @ 127711055 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @ 127711055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.109706881638410640022689970648054256389187779950537506006808457031768437050120
    Line 101, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 512254080 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 512254080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.5342944001830061691072858857477788728839405205851012874990797041596814559156
    Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  89299100 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @  89299100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 1.kmac_sideload_invalid.26813890267974148672743463960404821460708110296343979531954179477847770034286
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10103057074 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3d3e2000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10103057074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.kmac_sideload_invalid.5826001846669112535312217171952631078913641234330465661789892140744851328481
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10194260633 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1768e000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10194260633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 11.kmac_sideload_invalid.29205265020151786829336915485613921368925697271799805651745290565434472361834
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10257057743 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x63f4e000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10257057743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.kmac_sideload_invalid.113776352724752624646702085993392978757441089882667889858492286265100921302237
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10182176614 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5ce9d000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10182176614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 10.kmac_sideload_invalid.73643663225611318455038455129639371266290701708382311349893819186693703887518
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10111618310 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe2115000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10111618310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 33.kmac_sideload_invalid.59800849874165607101178857422693683285707021088133650844575138736116547254939
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10019687483 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xae9a7000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10019687483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 12.kmac_sideload_invalid.89790411505738890002181007021295170319766520445406701117530568062738765525196
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10090614710 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc6c70000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10090614710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 46.kmac_sideload_invalid.27691829143590822613424036477119528557516477850279464379468381561389030033308
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10295081880 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9f744000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10295081880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 23.kmac_sideload_invalid.7837219212834389739451854768368984546522547225394935499874376300452335460184
    Line 93, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10375804595 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x74473000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10375804595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 32.kmac_sideload_invalid.110464543021254592427971809436431419607669803287901943077265905197489920398069
    Line 94, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10134357980 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x601cc000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10134357980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 0.kmac_sideload_invalid.60522856742054048454651691838243839568941831697794193321584150406370032389132
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10041962519 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb14b2000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10041962519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 3.kmac_sideload_invalid.99782449010656457156606821248747599285677364010164660577115693572872492916011
    Line 98, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10123748003 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe1fc5000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
  UVM_INFO @ 10123748003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 4.kmac_sideload_invalid.26003978256421117141103733103800831546681152247949210914918728172292837880209
    Line 103, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10364283948 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6b410000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
  UVM_INFO @ 10364283948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 14.kmac_sideload_invalid.54732377867757228144484221762822223077201708435830135681165504408419259437440
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10078459368 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe0b48000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10078459368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 27.kmac_sideload_invalid.99432457885625665519373412876522892285079107136905366959445358132057144298418
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10084017227 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4297b000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10084017227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 44.kmac_sideload_invalid.49145314228361059434600150939717810420334216331165064335214323756500703650108
    Line 97, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10289481849 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x41fb5000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10289481849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```