OTBN Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	50.000s	37.899us	1	1	100.00
V1	single_binary	otbn_single	2.700m	3.117ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	20.261us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	68.245us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	256.095us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	60.187us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	40.151us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	68.245us	20	20	100.00
		otbn_csr_aliasing	7.000s	60.187us	5	5	100.00
V1	mem_walk	otbn_mem_walk	31.000s	1.246ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	417.302us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.167m	266.649us	10	10	100.00
V2	multi_error	otbn_multi_err	1.033m	598.187us	1	1	100.00
V2	back_to_back	otbn_multi	2.000m	321.547us	10	10	100.00
V2	stress_all	otbn_stress_all	2.533m	476.656us	10	10	100.00
V2	lc_escalation	otbn_escalate	54.000s	173.517us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	14.000s	38.938us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	27.000s	98.935us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	79.181us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	21.290us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	2.119ms	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	2.119ms	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	20.261us	5	5	100.00
		otbn_csr_rw	7.000s	68.245us	20	20	100.00
		otbn_csr_aliasing	7.000s	60.187us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	197.291us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	20.261us	5	5	100.00
		otbn_csr_rw	7.000s	68.245us	20	20	100.00
		otbn_csr_aliasing	7.000s	60.187us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	197.291us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	20.000s	152.018us	10	10	100.00
		otbn_dmem_err	20.000s	61.084us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	118.603us	5	5	100.00
		otbn_controller_ispr_rdata_err	15.000s	263.486us	5	5	100.00
		otbn_mac_bignum_acc_err	27.000s	215.390us	5	5	100.00
		otbn_urnd_err	14.000s	24.239us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	13.000s	31.674us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	42.821us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	14.916us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
		otbn_tl_intg_err	40.000s	205.100us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	234.543us	18	20	90.00
V2S	prim_fsm_check	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	50.000s	37.899us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	20.000s	61.084us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	20.000s	152.018us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	40.000s	205.100us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	54.000s	173.517us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	20.000s	152.018us	10	10	100.00
		otbn_dmem_err	20.000s	61.084us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	38.938us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	31.674us	5	5	100.00
		otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	20.000s	152.018us	10	10	100.00
		otbn_dmem_err	20.000s	61.084us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	38.938us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	31.674us	5	5	100.00
		otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	54.000s	173.517us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	20.000s	152.018us	10	10	100.00
		otbn_dmem_err	20.000s	61.084us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	38.938us	5	5	100.00
		otbn_illegal_mem_acc	13.000s	31.674us	5	5	100.00
		otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	22.279us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	14.000s	25.475us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.200m	858.877us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.200m	858.877us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	25.000s	79.065us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	31.000s	336.208us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	23.306us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	18.000s	23.306us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	73.277us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.000m	321.547us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	40.000s	130.090us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.700m	3.117ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.383m	2.135ms	4	5	80.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.583m	9.894ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			571	585	97.61

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.10	99.64	95.93	99.73	93.12	93.48	100.00	97.61	100.00

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

  • Test otbn_sec_wipe_err has 3 failures.

    • 0.otbn_sec_wipe_err.89100225025185323834537751887924716822092144348976866124805934213328722710425
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 73276972 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  73276972 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  73276972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.otbn_sec_wipe_err.76839816005796032385996136151606170042558644312031296357046024020393523421373
      Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10779470 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  10779470 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  10779470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

  • Test otbn_escalate has 2 failures.

    • 3.otbn_escalate.53484874955056247242598353041660535157403788099460799123285983536151574617207
      Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_escalate/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42433616 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  42433616 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  42433616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 38.otbn_escalate.47403345922636981344151312626032049398341550003870272097838080926192446416913
      Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/38.otbn_escalate/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22530878 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  22530878 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  22530878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:908) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:

  • Test otbn_stress_all_with_rand_reset has 4 failures.

    • 0.otbn_stress_all_with_rand_reset.114989475076159490816696668752458070318339530028984451545954797001007733550080
      Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 289663431 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 289663431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.otbn_stress_all_with_rand_reset.70222782052402999928804696741345948025970993534264156990534994136482959794042
      Line 314, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1126037326 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1126037326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 3.otbn_stress_all_with_rand_reset.51319464516231846580875109456187375931579035829235940882022771280322923774925
      Line 283, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 1300557329 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 1300557329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 18.otbn_passthru_mem_tl_intg_err.63141271623024617221282713035914366306943808719152977685436610180542245141687
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/18.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   2524657 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @   2524657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 1.otbn_sec_cm.91396682821033389300045965777134902096721966137531305590777281260233926965006
      Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 31609542 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 31609542 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  31609542 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  31609542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 2.otbn_partial_wipe.23324539462958571284128601909800565846050331072435660964064703778725936825453
      Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 7251901 PS) Assertion tb.MatchingStatus_A has failed
        UVM_ERROR @   7251901 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
        UVM_INFO @   7251901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 8.otbn_passthru_mem_tl_intg_err.99292296947615028590442094950035383215032847034035946804945749807794785019534
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   2545955 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @   2545955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---