ROM_CTRL/32KB Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.260s	139.444us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.420s	321.664us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.600s	172.069us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.950s	289.243us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.240s	1.022ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.540s	193.110us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.600s	172.069us	20	20	100.00
		rom_ctrl_csr_aliasing	5.240s	1.022ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.300s	190.881us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	5.620s	556.412us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.550s	315.882us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	25.240s	722.590us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.450s	219.813us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.350s	168.172us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.880s	202.389us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.880s	202.389us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.420s	321.664us	5	5	100.00
		rom_ctrl_csr_rw	5.600s	172.069us	20	20	100.00
		rom_ctrl_csr_aliasing	5.240s	1.022ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	5.770s	542.458us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.420s	321.664us	5	5	100.00
		rom_ctrl_csr_rw	5.600s	172.069us	20	20	100.00
		rom_ctrl_csr_aliasing	5.240s	1.022ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	5.770s	542.458us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.760s	841.507us	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.154m	912.613us	5	5	100.00
		rom_ctrl_tl_intg_err	41.130s	387.350us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.154m	912.613us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.154m	912.613us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.154m	912.613us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.154m	912.613us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.260s	139.444us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.260s	139.444us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.260s	139.444us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	41.130s	387.350us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
		rom_ctrl_kmac_err_chk	7.450s	219.813us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.861m	3.016ms	16	20	80.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.760s	841.507us	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.154m	912.613us	5	5	100.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.626m	21.434ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	100.00	99.41	100.00	100.00	100.00	98.97	99.05

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.109677229930384245186463297277624699071387026655070956782187917288172840007134
      Line 114, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 4926926654 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 4926926654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.rom_ctrl_corrupt_sig_fatal_chk.85153117687806675135585179408311618212711416963433496466030581436934714580156
      Line 115, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/7.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 6573740672 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 6573740672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly has 1 failures:
  • Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.

    • 15.rom_ctrl_passthru_mem_tl_intg_err.9294575244319970682726644657656963191070371930402537296052893253297815162937
      Line 80, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_ERROR @  84858302 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal triggered unexpectedly
        UVM_INFO @  84858302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---