RV_TIMER Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	48.647m	808.019ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.250s	16.617us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.300s	14.106us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.670s	697.219us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.500s	38.534us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	3.290s	157.793us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.300s	14.106us	20	20	100.00
		rv_timer_csr_aliasing	2.500s	38.534us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	14.546m	117.911ms	49	50	98.00
V2	disabled	rv_timer_disabled	5.257m	516.564ms	46	50	92.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	14.759m	3.775s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	14.759m	3.775s	50	50	100.00
V2	stress	rv_timer_stress_all	1.063h	2.328s	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.250s	19.939us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.900s	886.123us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.900s	886.123us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.250s	16.617us	5	5	100.00
		rv_timer_csr_rw	2.300s	14.106us	20	20	100.00
		rv_timer_csr_aliasing	2.500s	38.534us	5	5	100.00
		rv_timer_same_csr_outstanding	2.480s	36.248us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.250s	16.617us	5	5	100.00
		rv_timer_csr_rw	2.300s	14.106us	20	20	100.00
		rv_timer_csr_aliasing	2.500s	38.534us	5	5	100.00
		rv_timer_same_csr_outstanding	2.480s	36.248us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	rv_timer_sec_cm	2.450s	185.609us	5	5	100.00
		rv_timer_tl_intg_err	2.920s	258.907us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.920s	258.907us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.173m	5.391ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			582	620	93.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.13	99.65	99.08	92.06	--	99.13	99.68	99.20

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
  • Test rv_timer_stress_all_with_rand_reset has 33 failures.

    • 2.rv_timer_stress_all_with_rand_reset.34601813178525157512479452655410766434828825883445557511637544652470837593958
      Line 194, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18552236412 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18552236412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.rv_timer_stress_all_with_rand_reset.37611727652112654293148065482983577668412340280434151871278974423152168857654
      Line 221, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17259461029 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17259461029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 31 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
  • Test rv_timer_disabled has 4 failures.

    • 15.rv_timer_disabled.21154588339570977894169773187029298341093111991239397842709827610772382769040
      Line 73, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/15.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 16.rv_timer_disabled.1005645521675408683543928165281664645822089395581627584910254558377354104841
      Line 73, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/16.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

  • Test rv_timer_random_reset has 1 failures.

    • 19.rv_timer_random_reset.21574137409718238741147979745842488668081046824554997421903715265612200474282
      Line 74, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/19.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---