SPI_DEVICE/1R1W Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.899m	140.590ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.490s	76.823us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.880s	107.361us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.380s	5.078ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.360s	1.114ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.380s	226.489us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.880s	107.361us	20	20	100.00
		spi_device_csr_aliasing	22.360s	1.114ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.340s	21.882us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.600s	241.189us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.920s	50.702us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.740s	1.434us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.810s	1.684us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	9.540s	429.589us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.540s	429.589us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.080s	19.273ms	50	50	100.00
		spi_device_tpm_sts_read	2.850s	98.551us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.700s	18.331ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.100s	49.629ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.730s	32.935ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.730s	32.935ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.240s	16.751ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.240s	16.751ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.240s	16.751ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.240s	16.751ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.240s	16.751ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	30.430s	4.590ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.875m	15.241ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.875m	15.241ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.875m	15.241ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.020s	3.987ms	50	50	100.00
		spi_device_read_buffer_direct	14.830s	6.036ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.875m	15.241ms	50	50	100.00
		spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.470m	70.060ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	27.860s	14.740ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	27.860s	14.740ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.899m	140.590ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.034m	68.177ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.699m	110.497ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.830s	11.730us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.480s	47.099us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.410s	89.164us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.410s	89.164us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.490s	76.823us	5	5	100.00
		spi_device_csr_rw	3.880s	107.361us	20	20	100.00
		spi_device_csr_aliasing	22.360s	1.114ms	5	5	100.00
		spi_device_same_csr_outstanding	6.230s	210.427us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.490s	76.823us	5	5	100.00
		spi_device_csr_rw	3.880s	107.361us	20	20	100.00
		spi_device_csr_aliasing	22.360s	1.114ms	5	5	100.00
		spi_device_same_csr_outstanding	6.230s	210.427us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.810s	1.124ms	5	5	100.00
		spi_device_tl_intg_err	19.730s	867.905us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.730s	867.905us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.684m	165.193ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.22	83.25	89.36	98.37	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.53711735850101497519094955348375522918287981885848083019141168203655359715441
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2772664 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[80])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2772664 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2772664 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[976])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.38253459631039518141052113004911808315850274170191003743151467101821017216029
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    980606 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[10])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    980606 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    980606 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[906])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9019859287493572841263880985255482378689834965802415738091936097158520236592
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1144989 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1144989 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1154989 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb776f2 [101101110111011011110010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1154989 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xb776f2 [101101110111011011110010] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])