SPI_HOST Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.350m	102.876ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	32.066us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	42.519us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	902.761us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	56.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	104.811us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	42.519us	20	20	100.00
		spi_host_csr_aliasing	5.000s	56.883us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	14.924us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	27.574us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	44.000s	34.153us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.033m	13.428ms	50	50	100.00
		spi_host_error_cmd	42.000s	107.618us	50	50	100.00
		spi_host_event	6.100m	12.364ms	50	50	100.00
V2	clock_rate	spi_host_speed	47.000s	1.097ms	49	50	98.00
V2	speed	spi_host_speed	47.000s	1.097ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	47.000s	1.097ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	13.967m	73.403ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	41.000s	731.936us	50	50	100.00
V2	cpol_cpha	spi_host_speed	47.000s	1.097ms	49	50	98.00
V2	full_cycle	spi_host_speed	47.000s	1.097ms	49	50	98.00
V2	duplex	spi_host_smoke	10.350m	102.876ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	10.350m	102.876ms	50	50	100.00
V2	stress_all	spi_host_stress_all	5.183m	15.074ms	49	50	98.00
V2	spien	spi_host_spien	3.950m	47.742ms	50	50	100.00
V2	stall	spi_host_status_stall	6.083m	29.091ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	54.000s	2.821ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.033m	13.428ms	50	50	100.00
V2	alert_test	spi_host_alert_test	31.000s	24.541us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	18.429us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	103.496us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	103.496us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	32.066us	5	5	100.00
		spi_host_csr_rw	5.000s	42.519us	20	20	100.00
		spi_host_csr_aliasing	5.000s	56.883us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	21.567us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	32.066us	5	5	100.00
		spi_host_csr_rw	5.000s	42.519us	20	20	100.00
		spi_host_csr_aliasing	5.000s	56.883us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	21.567us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	63.816us	20	20	100.00
		spi_host_sec_cm	35.000s	327.707us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	63.816us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	42.050m	200.000ms	2	10	20.00
		TOTAL			828	840	98.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.30	96.78	93.31	98.70	94.71	88.02	100.00	96.86	91.56

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:

  • Test spi_host_upper_range_clkdiv has 4 failures.

    • 3.spi_host_upper_range_clkdiv.27049949613793909044819986694212355093961099801944319833278302097139836323561
      Line 179, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004852862 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4b290454, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004852862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.spi_host_upper_range_clkdiv.82628914731560607878714643691395043379817700887442465018089624457834541259295
      Line 155, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100001709124 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8776f254, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100001709124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.22309796606257117214693402345201717065307453017310698183891365807912516362896
      Line 161, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 175730771375 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe89c67d4, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
        UVM_INFO @ 175730771375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 1.spi_host_upper_range_clkdiv.22283406617705431021704302990673150331992504780783562439319776584357410474244
      Line 177, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 7.spi_host_upper_range_clkdiv.52547837146723508667982856258448786705100432552680615062299983432865341537402
      Line 143, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100010493545 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xc2b07914, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
        UVM_INFO @ 100010493545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=82) has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 8.spi_host_speed.96168606524748333141097447637215405090284910801640959331806326111550673473947
      Line 461, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_speed/latest/run.log

        UVM_FATAL @ 10077198126 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xb2949cd4, Comparison=CompareOpEq, exp_data=0x0, call_count=82)
        UVM_INFO @ 10077198126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 8.spi_host_upper_range_clkdiv.23507986579588407637111047954302754499809210007265087493700811754136415403945
      Line 149, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100007982908 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcc562194, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
        UVM_INFO @ 100007982908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:

  • Test spi_host_stress_all has 1 failures.

    • 18.spi_host_stress_all.33593127221533871615663083901630745983392749952339449840429851505676796227311
      Line 188, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/18.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 15073970272 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x7bf75fd4, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
        UVM_INFO @ 15073970272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test spi_host_sw_reset has 1 failures.

    • 20.spi_host_sw_reset.68287964672306169677101958701895965999596132084580862717343943827548810921009
      Line 160, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/20.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 10002873333 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x88ec6ed4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
        UVM_INFO @ 10002873333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=172) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 20.spi_host_status_stall.89324808753144153909562891807846642483779184603943755111816625818701329478509
      Line 828, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/20.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 17757059124 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa8d99a94, Comparison=CompareOpEq, exp_data=0x0, call_count=172)
        UVM_INFO @ 17757059124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---