SRAM_CTRL/MAIN Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.429m	1.022ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.980s	27.942us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.070s	14.407us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.630s	43.046us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.000s	15.720us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.740s	409.870us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.070s	14.407us	20	20	100.00
		sram_ctrl_csr_aliasing	2.000s	15.720us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.579m	230.315ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.787m	9.982ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	15.561m	83.972ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.338m	7.395ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	38.474m	919.815ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.801m	63.751ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.469m	67.705ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.580m	61.888ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.616m	2.951ms	50	50	100.00
		sram_ctrl_partial_access_b2b	7.843m	18.115ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.869m	3.324ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.285m	833.963us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.689m	931.435us	50	50	100.00
V2	regwen	sram_ctrl_regwen	15.440m	71.974ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.370s	4.216ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.839h	344.317ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.160s	40.245us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.760s	616.282us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.760s	616.282us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.980s	27.942us	5	5	100.00
		sram_ctrl_csr_rw	2.070s	14.407us	20	20	100.00
		sram_ctrl_csr_aliasing	2.000s	15.720us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.150s	14.690us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.980s	27.942us	5	5	100.00
		sram_ctrl_csr_rw	2.070s	14.407us	20	20	100.00
		sram_ctrl_csr_aliasing	2.000s	15.720us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.150s	14.690us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	48.440s	54.062ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.070s	5.549us	0	5	0.00
		sram_ctrl_tl_intg_err	3.460s	3.099ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.070s	5.549us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.460s	3.099ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.440m	71.974ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.440m	71.974ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.070s	14.407us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.580m	61.888ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.580m	61.888ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.580m	61.888ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.469m	67.705ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.640s	13.409ms	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	48.440s	54.062ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.890s	2.872ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.429m	1.022ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.429m	1.022ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.580m	61.888ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.070s	5.549us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.469m	67.705ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.070s	5.549us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.070s	5.549us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.429m	1.022ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.070s	5.549us	0	5	0.00
V2S		TOTAL			125	145	86.21
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.519m	4.331ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1170	1190	98.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	99.29	93.01	85.18	100.00	98.07	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 3.sram_ctrl_readback_err.93404196538989954754476462888922771776208679523884470480597445495647279714870
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 3867701444 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x42) != exp (0x54)
        UVM_INFO @ 3867701444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.7964494274279195204827664924034268192491670314334417594119542330890697117304
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2434801274 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x23) != exp (0xa)
        UVM_INFO @ 2434801274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 2.sram_ctrl_mubi_enc_err.109919056344441637695305216507313804691344382915369379022929636971339640376394
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 676884018 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 676884018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_mubi_enc_err.23673668174632568167161758196640589336030819978801489568493513085027098918136
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 772724976 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 772724976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.12169499662904073048506916836614852834541354548784147535612876621080747648331
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3253327 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3253327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.79501474566727806753458097484634519473917789122572645699402868449659433916499
      Line 102, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5548793 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5548793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.90285734869837262156951511183516871809802301505820279138859391621661899121031
      Line 100, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7559921 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7559921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.56695478968816831896661395769663495904913207557164773664693112880911300524989
      Line 100, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10142191 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10142191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.97751978645755738283322790666031216598428438750883935418788247021062057667177
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3524785 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3524785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---