SRAM_CTRL/RET Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.506m	1.253ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.000s	37.456us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.960s	35.903us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.700s	526.994us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.910s	105.894us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.620s	162.851us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.960s	35.903us	20	20	100.00
		sram_ctrl_csr_aliasing	1.910s	105.894us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.140s	8.118ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.400s	1.444ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	18.982m	19.722ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.636m	4.271ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.347m	6.852ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	16.661m	5.145ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.860s	1.077ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.207m	305.017ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.267m	593.604us	50	50	100.00
		sram_ctrl_partial_access_b2b	7.857m	72.440ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.285m	135.363us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.469m	1.126ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.372m	1.476ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	17.483m	75.925ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.260s	201.006us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.055h	989.473ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.130s	13.501us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.710s	166.479us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.710s	166.479us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.000s	37.456us	5	5	100.00
		sram_ctrl_csr_rw	1.960s	35.903us	20	20	100.00
		sram_ctrl_csr_aliasing	1.910s	105.894us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.070s	20.416us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.000s	37.456us	5	5	100.00
		sram_ctrl_csr_rw	1.960s	35.903us	20	20	100.00
		sram_ctrl_csr_aliasing	1.910s	105.894us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.070s	20.416us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.600s	1.037ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.670s	7.661us	0	5	0.00
		sram_ctrl_tl_intg_err	3.450s	623.402us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.670s	7.661us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.450s	623.402us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	17.483m	75.925ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	17.483m	75.925ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.960s	35.903us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.207m	305.017ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.207m	305.017ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.207m	305.017ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.860s	1.077ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.580s	383.783us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.600s	1.037ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.710s	134.311us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.506m	1.253ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.506m	1.253ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.207m	305.017ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.670s	7.661us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.860s	1.077ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.670s	7.661us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.670s	7.661us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.506m	1.253ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.670s	7.661us	0	5	0.00
V2S		TOTAL			125	145	86.21
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.601m	1.595ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1170	1190	98.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	99.27	93.01	85.10	100.00	98.03	98.58	98.52

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 0.sram_ctrl_readback_err.61332442941480451167359256230199209447464109614934611617668399295864491303091
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 186545189 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x6c) != exp (0x27)
        UVM_INFO @ 186545189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_readback_err.98598284207291765503442383225792640575277154032894028560354145946068317785462
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 366058828 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x2f) != exp (0x4b)
        UVM_INFO @ 366058828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 15.sram_ctrl_mubi_enc_err.34413636628998786477915697243217484511191734242352330994263835009813269500775
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 153309704 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 153309704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 30.sram_ctrl_mubi_enc_err.92106620136816464848379289769249482739737685641673589256583834005364658605709
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/30.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  23033775 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  23033775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 1.sram_ctrl_sec_cm.106353231881595514307311171765173662983959126892894309082134826832441653762129
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   8399896 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   8399896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.3896236033517055132284521351587242537693773310047702653792716023947059338363
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  11141402 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  11141402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 3.sram_ctrl_sec_cm.5288855117203098007455895081277339721337148717643015112972472323010978708240
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3616411 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3616411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.75766640157428109824451378186382204281575251083976069380837154003606995965355
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @    944453 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @    944453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.59472814514515133343549609762629781485606601736352814738547959373679140362493
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7660904 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7660904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---