UART Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	36.500s	11.096ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.290s	15.481us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.370s	13.264us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.870s	167.601us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.260s	16.711us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.770s	22.182us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.370s	13.264us	20	20	100.00
		uart_csr_aliasing	2.260s	16.711us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.590m	141.178ms	50	50	100.00
V2	parity	uart_smoke	36.500s	11.096ms	50	50	100.00
		uart_tx_rx	4.590m	141.178ms	50	50	100.00
V2	parity_error	uart_intr	6.049m	245.853ms	50	50	100.00
		uart_rx_parity_err	3.775m	137.309ms	50	50	100.00
V2	watermark	uart_tx_rx	4.590m	141.178ms	50	50	100.00
		uart_intr	6.049m	245.853ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.458m	176.986ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.259m	138.908ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	10.250m	127.130ms	300	300	100.00
V2	rx_frame_err	uart_intr	6.049m	245.853ms	50	50	100.00
V2	rx_break_err	uart_intr	6.049m	245.853ms	50	50	100.00
V2	rx_timeout	uart_intr	6.049m	245.853ms	50	50	100.00
V2	perf	uart_perf	18.583m	25.761ms	50	50	100.00
V2	sys_loopback	uart_loopback	23.180s	7.315ms	50	50	100.00
V2	line_loopback	uart_loopback	23.180s	7.315ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.481m	89.467ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.509m	44.064ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	29.260s	7.078ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.129m	7.381ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.902m	146.317ms	50	50	100.00
V2	stress_all	uart_stress_all	21.649m	221.471ms	50	50	100.00
V2	alert_test	uart_alert_test	2.170s	24.209us	50	50	100.00
V2	intr_test	uart_intr_test	2.460s	11.895us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	4.000s	147.723us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	4.000s	147.723us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.290s	15.481us	5	5	100.00
		uart_csr_rw	2.370s	13.264us	20	20	100.00
		uart_csr_aliasing	2.260s	16.711us	5	5	100.00
		uart_same_csr_outstanding	2.450s	111.466us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.290s	15.481us	5	5	100.00
		uart_csr_rw	2.370s	13.264us	20	20	100.00
		uart_csr_aliasing	2.260s	16.711us	5	5	100.00
		uart_same_csr_outstanding	2.450s	111.466us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	2.380s	79.699us	5	5	100.00
		uart_tl_intg_err	2.920s	75.503us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.920s	75.503us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.489m	33.044ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1318	1320	99.85

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.17	98.25	91.55	--	98.15	100.00	99.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:811) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

82.uart_stress_all_with_rand_reset.29268492930331080704620511465237833357520562735720952778199896116239222096300
Line 101, in log /nightly/runs/scratch/master/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 554906440 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 554906440 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 555010610 ps: (cip_base_vseq.sv:835) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/10

UVM_ERROR (cip_base_vseq.sv:907) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

92.uart_stress_all_with_rand_reset.64936295772252357696469199931148449670012828052543360311441642125832651459336
Line 136, in log /nightly/runs/scratch/master/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3059525095 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3059532848 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3059532848 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 3059536084 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1