CHIP Simulation Results

Friday April 11 2025 17:39:13 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.820m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.820m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.497m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	3.015m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.593m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.248m	6.421ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.248m	6.421ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.248m	6.421ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.712m		0	3	0.00
		chip_sw_example_manufacturer	4.760m		0	3	0.00
		chip_sw_example_concurrency	5.719m	5.856ms	3	3	100.00
		chip_sw_uart_smoketest_signed	26.499s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	17.450s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	16.030s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	16.030s		0	3	0.00
V1	xbar_smoke	xbar_smoke	36.050s	69.293us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.796m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.771m	7.612ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.136m	5.586ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.135m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.116m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	2.605m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	2.658m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	5.160s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.160s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.753m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.584m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.688m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.688m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.428m	3.674ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.541m	4.333ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.936m	5.713ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	1.472m		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	29.123s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	26.631m	30.903ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.685m	6.134ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	31.508m	18.016ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	31.508m	18.016ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	17.912s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.639s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	19.639s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	1.113m		0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.598m	4.473ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.362m	5.938ms	3	3	100.00
		chip_sw_aes_idle	6.251m	4.268ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.103m	3.737ms	3	3	100.00
		chip_sw_kmac_idle	4.608m	4.589ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	20.164s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	19.849s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	52.987s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	43.071s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	18.549s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	1.259m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	39.482s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.011m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.083m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.124s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	34.211s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.549s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	1.259m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	39.482s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.011m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.083m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.124s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	34.211s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.363s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.432m	10.180us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.225m	10.240us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.128m	10.400us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.009m	10.280us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	49.857s		0	3	0.00
		chip_sw_clkmgr_jitter	5.619m	5.109ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.279m	5.006ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	54.259s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	55.380s	10.300us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.284m	10.220us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.335m	10.200us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.393m	10.180us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.334m	10.320us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	20.789s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	54.702s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	22.393s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	40.568s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	37.043m	17.324ms	29	100	29.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.587m	16.376ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	19.639s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	15.022s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.587m	16.376ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	26.065s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	22.021s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	37.355s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	37.379s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.017m		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	37.043m	17.324ms	29	100	29.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.936m	5.713ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	36.220m	20.016ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.965m	12.018ms	0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	30.655m	30.017ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.808m	4.483ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	37.043m	17.324ms	29	100	29.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	19.923s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	1.296m		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	37.043m	17.324ms	29	100	29.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	19.204s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	30.655m	30.017ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	34.075s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.194m		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	1.350m		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	48.654s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	23.706s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	45.698s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	1.296m		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.071m		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	10.460m	20.010ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.022m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	57.551s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	49.323s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	39.984s		0	3	0.00
		chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	9.648m	20.010ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	14.721m	13.677ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	32.065s		0	3	0.00
		chip_prim_tl_access	19.792m	19.856ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.549s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	1.259m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	39.482s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.011m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.083m		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.124s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	34.211s		0	3	0.00
		chip_rv_dm_lc_disabled	26.631m	30.903ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.858m	4.974ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.432m	10.180us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.582m	5.502ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	6.251m	4.268ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.971m	5.078ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.225m	10.240us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.103m	3.737ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.548m	4.496ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.255m	5.026ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.009m	10.280us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	9.648m	20.010ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	53.610s	10.280us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.283m	3.430ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.608m	4.589ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1.489m		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1.489m		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	37.535s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.004m	6.050ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.577m		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	9.648m	20.010ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.128m	10.400us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.745m		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.363s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.362m	5.938ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.362m	5.938ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.362m	5.938ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.945m	6.476ms	2	3	66.67
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	14.721m	13.677ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	14.721m	13.677ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	16.598m	7.694ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	49.857s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	32.065s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	37.043m	17.324ms	29	100	29.00
		chip_sw_data_integrity_escalation	4.688m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.945m	6.476ms	2	3	66.67
		chip_sw_keymgr_dpe_key_derivation	9.648m	20.010ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	16.598m	7.694ms	0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	6.490m	6.077ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.945m	6.476ms	2	3	66.67
		chip_sw_keymgr_dpe_key_derivation	9.648m	20.010ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	16.598m	7.694ms	0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	6.490m	6.077ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	18.082s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.071m		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.022m		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	57.551s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	49.323s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	39.984s		0	3	0.00
		chip_sw_lc_ctrl_transition	47.763s		0	15	0.00
		chip_prim_tl_access	19.792m	19.856ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	19.792m	19.856ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	49.554s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	1.442m		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	54.702s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.363s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.432m	10.180us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.225m	10.240us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.128m	10.400us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.009m	10.280us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	49.857s		0	3	0.00
		chip_sw_clkmgr_jitter	5.619m	5.109ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.482m	6.591ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.482m	6.591ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.310m	4.541ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.090m	5.566ms	3	3	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.597m	3.641ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	11.417m	6.295ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.820m	5.047ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.944m	3.587ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	6.490m	6.077ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	36.220m	20.016ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	36.220m	20.016ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	6.011m	5.194ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.925m	5.475ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.490m	3.999ms	3	3	100.00
		chip_sw_csrng_smoketest	5.654m	3.790ms	3	3	100.00
		chip_sw_gpio_smoketest	6.800m	5.744ms	3	3	100.00
		chip_sw_hmac_smoketest	8.152m	6.374ms	3	3	100.00
		chip_sw_kmac_smoketest	7.050m	5.746ms	3	3	100.00
		chip_sw_otbn_smoketest	9.602m	4.765ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.028m	5.288ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.301m	5.507ms	3	3	100.00
		chip_sw_rv_timer_smoketest	7.437m	5.739ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.882m	3.915ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.005m	5.065ms	3	3	100.00
		chip_sw_uart_smoketest	6.368m	4.981ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	22.957s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	26.499s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.796m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	20.415s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.083m	4.390ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.181m	3.736ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.373m	5.969ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	6.273m	5.423ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	15.838s		0	3	0.00
		chip_rv_dm_lc_disabled	26.631m	30.903ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	40.044s		0	3	0.00
		chip_sw_lc_walkthrough_prod	19.953s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	35.644s		0	3	0.00
		chip_sw_lc_walkthrough_rma	15.733s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	15.838s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.514m		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	31.719s		0	3	0.00
		rom_volatile_raw_unlock	24.892s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	23.083s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.720m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.620m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.992m	5.132ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.992m	5.132ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	16.030s		0	3	0.00
		chip_same_csr_outstanding	14.860s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	16.030s		0	3	0.00
		chip_same_csr_outstanding	14.860s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	5.272m	586.037us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	16.000s	13.593us	100	100	100.00
		xbar_smoke_large_delays	9.427m	2.849ms	100	100	100.00
		xbar_smoke_slow_rsp	11.008m	2.350ms	100	100	100.00
		xbar_random_zero_delays	2.106m	78.004us	100	100	100.00
		xbar_random_large_delays	36.814m	14.149ms	100	100	100.00
		xbar_random_slow_rsp	57.788m	14.559ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.986m	243.044us	100	100	100.00
		xbar_error_and_unmapped_addr	2.597m	221.758us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.516m	501.412us	100	100	100.00
		xbar_error_and_unmapped_addr	2.597m	221.758us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	7.725m	921.916us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.788m	17.406ms	78	100	78.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	3.766m	429.856us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	41.178m	5.849ms	100	100	100.00
		xbar_stress_all_with_error	40.509m	5.972ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	48.748m	1.802ms	98	100	98.00
		xbar_stress_all_with_reset_error	57.982m	6.578ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	23.869s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.591s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	17.401s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	19.640s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	17.352s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	17.522s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	17.960s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	17.180s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.210s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.617s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	18.093s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.412s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.627s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.939s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.431s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.748s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15.526s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.297s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.992s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.050s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.161s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.789s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.854s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.646s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.880s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.343s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.786s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.356s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.865s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.730s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.167s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.929s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.031s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	17.892s		0	3	0.00
		rom_e2e_asm_init_dev	14.767s		0	3	0.00
		rom_e2e_asm_init_prod	17.043s		0	3	0.00
		rom_e2e_asm_init_prod_end	18.144s		0	3	0.00
		rom_e2e_asm_init_rma	18.218s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	16.864s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	17.903s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.518s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	17.255s		0	3	0.00
V2		TOTAL			1839	2429	75.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.095m	4.025ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.863m	5.685ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.800s		0	1	0.00
		rom_e2e_jtag_debug_dev	13.993s		0	1	0.00
		rom_e2e_jtag_debug_rma	17.690s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	17.569s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	37.043m	17.324ms	29	100	29.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	39.688s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.478m	15.825ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	27.763s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	43.070s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.800s		0	1	0.00
		rom_e2e_jtag_debug_dev	13.993s		0	1	0.00
		rom_e2e_jtag_debug_rma	17.690s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	16.782s		0	1	0.00
		rom_e2e_jtag_inject_dev	17.583s		0	1	0.00
		rom_e2e_jtag_inject_rma	18.133s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.609m		0	3	0.00
V3		TOTAL			0	20	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	24.426m	12.529ms	2	3	66.67
		chip_plic_all_irqs_0	11.532m	5.917ms	3	3	100.00
		chip_plic_all_irqs_10	14.749m	7.446ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.123m	5.013ms	3	3	100.00
		chip_sw_dma_abort	5.712m	4.253ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	17.256s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	18.832s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	17.871s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	18.596s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	18.291s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	17.867s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	18.173s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	17.427s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	18.236s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	22.723s		0	3	0.00
		chip_sw_mbx_smoketest	6.786m	4.234ms	3	3	100.00
		TOTAL			1965	2659	73.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.53	74.65	78.15	66.07	--	80.98	67.91	85.42

Failure Buckets

Job returned non-zero exit code has 478 failures:

Test chip_sw_example_rom has 3 failures.

0.chip_sw_example_rom.24408157394865516031148312854545773276448260109678819200218038162683481673359
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (2883b1)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (cecd6a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 78.909s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_rom.19227975229906931589132361881815360748559484000311961440946129472609724338172
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (b13a3c)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (45a62f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 2.616s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.77566266376953202623222512107778143253752310873036815205641367378169106156804
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (ed9a8d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 259.843s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.87812058169456566506244045010430840687990411145917151075238323932660864056144
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (5481bf)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 7.329s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.58337818801283478792281488675419790673492263633023423778988030960706943834941
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (900aa1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 263.256s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.41446276842333281051347291688376099217561284804751720462312345573674900978138
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (378337)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 3.803s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.10508055769308858259338168952966406834166197669025789790884205138286091949288
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (489f8a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 267.838s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.52602063042428572310215711535697806686168176420490045405699870209538480210447
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (ed29f1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 14.339s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.33235792443454345936745015432123565509879696675197566145305101594028568661115
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (f741ae)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 79.626s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.45575583468873494302929789395720138782515559399402164315456939730750681332484
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (1c670b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 35.942s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 138 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 69 failures:
- Test chip_sw_all_escalation_resets has 69 failures.
  - 4.chip_sw_all_escalation_resets.71613645181767369831270563331408360534795747654717922310073572713000631686089
    Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 16878.651918 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 16878.651918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.chip_sw_all_escalation_resets.9892014067440195815464044152473530311835985601829021685615135778845292238072
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 17620.025250 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17620.025250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 67 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.111094096626300964355323448674143431076244037793165208070844630004201276333478
    Line 642, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.5182030601986648840061375497672651632042646495523532101057114456510207313577
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.13441644019627348216344090295265498933343847630639943008350930949363878784348
    Line 626, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.83257978260284215554664143435567447354900309548124022904887247889141254062011
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.11475450313151089086787566436785626116615266950493501063517705454208248060306
    Line 705, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.114698596535190366328044688111253514670385182636908941619462883999237998419430
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.44599267642949803201077009443533989884196130135043189829489399714764059997280
    Line 535, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.7567230432325846697807093865708227887270575803054915410011980610330684682101
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.29469816732637138658647857142733634823277349225421707893386492771284050693253
    Line 510, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.77235095313031647339034980098582605555172214499924768659579986301482374269024
    Line 451, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.
Job timed out after * minutes has 24 failures:
- Test xbar_access_same_device_slow_rsp has 22 failures.
  - 0.xbar_access_same_device_slow_rsp.88050484274859338003939414026574584042616418899137502496080020232233610362867
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.xbar_access_same_device_slow_rsp.103713683977881943671932089499961057502609237654332085577309720437720359338164
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 20 more failures.
- Test xbar_stress_all_with_rand_reset has 2 failures.
  - 11.xbar_stress_all_with_rand_reset.90646600961962390865083253260100091274753234733982123891296879571877264330886
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 64.xbar_stress_all_with_rand_reset.28416182044432606750775308871164033102448442392780095394902958902359510667412
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/64.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 11 failures:

Test chip_sw_rstmgr_sw_req has 3 failures.

0.chip_sw_rstmgr_sw_req.47966095845671020895041012094307342140083564142260604009705144277050732182575
Line 686, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12017.510837 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.510837 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_sw_req.64023945493684110433408582564382913790340424534028358268123425598998697495021
Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12017.666552 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.666552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.110939143315706232985531420607470422849032491653318624412722204829341725211068
Line 639, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.089063 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.089063 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.34042491810598847740434357967252132171832248126008779465932251122107202684333
Line 474, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.665912 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.665912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.66668753022389028572421968110226226677792368160208417250114406385881241050348
Line 705, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.997207 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.997207 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.40841378848075348617127043825283723433261269358624796642156296252772849455088
Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.064510 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.064510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_rstmgr_alert_info has 2 failures.

1.chip_sw_rstmgr_alert_info.27916925574435689012116902590225951645665735807642788747401132940512749144068
Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30024.461675 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30024.461675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_rstmgr_alert_info.110736177186171899030047022091402783376262863275408914831391518546270110631193
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30022.146491 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30022.146491 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.58732156697278200983572509399107593642941386198464468678776006308019623006649
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.33655093862179099255685167309720646070738868552425268673554291680171844802049
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 10 failures:

Test chip_tl_errors has 10 failures.

5.chip_tl_errors.9867587915209218477876252538274848176791356808365441110530733519013782024164
Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/5.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5683.226544 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5683.226544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.chip_tl_errors.65143182859518523444664578065070732046688391109764491772645461407986814574458
Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/7.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3903.490522 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3903.490522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.91869932096142738953477409878749768765100179027567531221397859366810783735056
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.31472033732994831003662350320576698638698844423381865956252164576778659269565
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.29760386496132811173752114567308849997242253736766898129413841373144432448052
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.88744794214259990814261090398729669401350569392135005267281186941767564679214
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.28310244504281167141460823418823467808751045535631114511147420723928444541549
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.101971664105994136754219451143499595091444866417715333405187428924915171778831
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.38478309333638903151940015531504832884890477701795336565882449988272733253250
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4295.551397 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'he28c4732  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h1  a_user: 'h248e2  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4295.551397 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.59267398835822151790923084841090796399453801182314913125354595915905851879552
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3674.051655 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h3b595fdd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h1  a_user: 'h248a8  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3674.051655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.95879376049672411325168811676038876508556668045509622844324184005465129155064
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4333.454625 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h9c2ad91d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h1  a_user: 'h248f0  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4333.454625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.90626547417268528788688766306183806757887778030552329141713583015824982360993
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5178.692593 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h297e55a4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h1  a_user: 'h248f0  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5178.692593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 4 failures:
- Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.48475757412033822160006736782989319736742427958896985089499995829302447546820
    Line 709, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.340001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_prod.70923756830963734837474092705772645871738409223098659196788811787016988001598
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.120001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 2.chip_sw_keymgr_dpe_key_derivation.43027780769924818763016119464487331671848132794179384469158382948375167852788
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.140001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.88121154102876683364289280241677232606985461274203060485535967399106577550523
    Line 626, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5317.672842 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5317.672842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.90615645013062896833363840318863147070563886726236332568776212992818271377899
    Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4782.093904 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4782.093904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.18550766997410645378796674335586797050594330652765433750769524095432679839917
Line 649, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 3687.802338 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3687.802338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.104223157458824497312156286193590562962787347735156767882479274688259985957905
Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 4540.610032 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4540.610032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.45064022399491820260041347932303379712565508324548024966006616584629916558293
    Line 723, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6560.178340 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6560.178340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.115106782783526516288464183600434944174568574794421011990722220042351972001832
    Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5222.161492 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5222.161492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.99658936198492735101410042657823942314238257596830997389266203218037231337440
    Line 556, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.30383943041059681105984043906031026472975935137072475289595802398020370025807
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:* = ErrorError has 3 failures:
- Test chip_sw_sram_ctrl_scrambled_access has 3 failures.
  - 0.chip_sw_sram_ctrl_scrambled_access.102953836884775646245533986699137985732875099288659814773614888735476424661797
    Line 630, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 6474.829812 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6474.829812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_sram_ctrl_scrambled_access.28873453249190128058775754390035097426346087327825419813242161223367165345687
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sram_ctrl_scrambled_access/latest/run.log
```
  UVM_ERROR @ 6660.458840 us: (sw_logger_if.sv:526) [sram_ctrl_scrambled_access_test_sim_dv(sw/device/tests/sram_ctrl_scrambled_access_test.c:472)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 6660.458840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.319771096658111036351249305877102531837856856881990260047010635213334963282
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4253.149530 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4253.149530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.71304883727106208097148720423365204180658295387897346582400784533135935347777
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 6042.337092 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 6042.337092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 2 failures.

0.chip_sw_keymgr_dpe_key_derivation.17776019431295512621211690336091082257668071608197467352584128035732308294005
Line 655, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6074.609560 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (111475509235080000126597536349114630616497139977303761614724625982912980097526 [0xf674e6fd0ec6338b11f7983df4e5f6650a0948da7c4b2a30769616c4573499f6] vs 77643179177215097425697642994841545509673249182430463204776112244319093667685 [0xaba87b69a1699a255fba13d09c153edc0b0c1a7e0d7cc4d80837f2c53d423765])
  UVM_INFO @ 6074.609560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.87549694323466101442061658032234790150660249668532545117042745070047810756701
Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9030.686320 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (95753091078160188083217410598440231001839140640979744357644415417734229776091 [0xd3b25437be94072e58ca1e79d23046de9dae34ae4660303721bebbaa1ed9d6db] vs 38554552618702747148231754227380334304606304483937204037541615090837071242762 [0x553d1a7d1a5a5077f348bfac5c0fe49c5f4067130965d0836074561d9faea60a])
  UVM_INFO @ 9030.686320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_rstmgr_cnsty_fault_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.23902781486126530629037955478665593235089014248716977420078865824494350752739
    Line 663, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  UVM_ERROR @ 17559.033080 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rstmgr_cnsty_fault_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17559.033080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.100199418657909689780627975121103083555605700996810514873375238744808943041636
    Line 549, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_ERROR @ 15824.691144 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 15824.691144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.97004466905054435437735743944806136501984137538069497849499922556426782171468
    Line 704, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 30017.208325 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.208325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36226) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: