AES/MASKED Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	142.222us	1	1	100.00
V1	smoke	aes_smoke	7.000s	95.285us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	323.471us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	76.925us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.146ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	302.871us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	65.350us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	76.925us	20	20	100.00
		aes_csr_aliasing	7.000s	302.871us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	95.285us	50	50	100.00
		aes_config_error	9.000s	329.118us	50	50	100.00
		aes_stress	1.033m	3.550ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	95.285us	50	50	100.00
		aes_config_error	9.000s	329.118us	50	50	100.00
		aes_stress	1.033m	3.550ms	50	50	100.00
V2	back2back	aes_stress	1.033m	3.550ms	50	50	100.00
		aes_b2b	1.033m	1.310ms	50	50	100.00
V2	backpressure	aes_stress	1.033m	3.550ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	95.285us	50	50	100.00
		aes_config_error	9.000s	329.118us	50	50	100.00
		aes_stress	1.033m	3.550ms	50	50	100.00
		aes_alert_reset	34.000s	3.411ms	49	50	98.00
V2	failure_test	aes_man_cfg_err	7.000s	181.838us	50	50	100.00
		aes_config_error	9.000s	329.118us	50	50	100.00
		aes_alert_reset	34.000s	3.411ms	49	50	98.00
V2	trigger_clear_test	aes_clear	11.000s	1.318ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	684.946us	1	1	100.00
V2	reset_recovery	aes_alert_reset	34.000s	3.411ms	49	50	98.00
V2	stress	aes_stress	1.033m	3.550ms	50	50	100.00
V2	sideload	aes_stress	1.033m	3.550ms	50	50	100.00
		aes_sideload	32.000s	1.476ms	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	1.115ms	50	50	100.00
V2	stress_all	aes_stress_all	13.067m	40.915ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	62.878us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	230.764us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	230.764us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	323.471us	5	5	100.00
		aes_csr_rw	5.000s	76.925us	20	20	100.00
		aes_csr_aliasing	7.000s	302.871us	5	5	100.00
		aes_same_csr_outstanding	6.000s	75.390us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	323.471us	5	5	100.00
		aes_csr_rw	5.000s	76.925us	20	20	100.00
		aes_csr_aliasing	7.000s	302.871us	5	5	100.00
		aes_same_csr_outstanding	6.000s	75.390us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	12.000s	487.769us	50	50	100.00
V2S	fault_inject	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	139.778us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	139.778us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	139.778us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	139.778us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	654.401us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	515.642us	5	5	100.00
		aes_tl_intg_err	6.000s	138.628us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	138.628us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	34.000s	3.411ms	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	139.778us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	95.285us	50	50	100.00
		aes_stress	1.033m	3.550ms	50	50	100.00
		aes_alert_reset	34.000s	3.411ms	49	50	98.00
		aes_core_fi	55.000s	10.020ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	139.778us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	163.501us	50	50	100.00
		aes_stress	1.033m	3.550ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.033m	3.550ms	50	50	100.00
		aes_sideload	32.000s	1.476ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	163.501us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	163.501us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	163.501us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	163.501us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	163.501us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.033m	3.550ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.033m	3.550ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	28.000s	4.058ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
		aes_ctr_fi	14.000s	10.020ms	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	28.000s	4.058ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.094ms	335	350	95.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	28.000s	4.058ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_ctr_fi	14.000s	10.020ms	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
		aes_ctr_fi	14.000s	10.020ms	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	34.000s	3.411ms	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
		aes_ctr_fi	14.000s	10.020ms	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
		aes_ctr_fi	14.000s	10.020ms	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_ctr_fi	14.000s	10.020ms	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	28.000s	4.058ms	50	50	100.00
		aes_control_fi	36.000s	10.014ms	282	300	94.00
		aes_cipher_fi	51.000s	10.094ms	335	350	95.71
V2S		TOTAL			950	985	96.45
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	32.000s	4.054ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1556	1602	97.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.41	98.59	96.43	99.43	95.71	98.07	100.00	98.96	99.20

Failure Buckets

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 33.aes_cipher_fi.59831576870704922080126128761819328799808781716212017794183316662312957173905
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007446917 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007446917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 57.aes_cipher_fi.59918669152045525288544129165142056144452150269316722088764510802252285782006
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015935982 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015935982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
Job timed out after * minutes has 13 failures:
- Test aes_control_fi has 12 failures.
  - 7.aes_control_fi.36714468484830295556300246048472472122912269944534673238072506775180993091137
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 26.aes_control_fi.68805610417978917911380004419709563431813425132971285063192899229154357605844
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 1 failures.
  - 198.aes_cipher_fi.38685886947056244303615063267151028159802102037200821760529694920384395750672
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/198.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.38226299878884013324636247515204084266368299640244051759830857648010507889077
Line 307, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1472059720 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1472059720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.41740619067355463597486633485974578405734902858231262245967981843467687723924
Line 275, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 157064182 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 157064182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 51.aes_control_fi.52082531303396176521463356269473338599510719358331853949502865693401974403458
    Line 134, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006143676 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006143676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 58.aes_control_fi.108470299097292575642837686594983983098478485524169235118266175850143182335820
    Line 145, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009198788 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009198788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.20448293080313490774024111603341936735938122098972493446993569936051546858735
    Line 174, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  62608461 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  62608461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.83495534057235973288152132890648717015567819564217448446057968162435946498223
    Line 238, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 763887959 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 763887959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_ctr_fi_vseq.sv:59) [aes_ctr_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_ctr_fi has 1 failures.
  - 6.aes_ctr_fi.34828067310807887425457523131343045719202467905877794817667851430866177065172
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_ctr_fi/latest/run.log
```
  UVM_FATAL @ 10020188063 ps: (aes_ctr_fi_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.aes_ctr_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020188063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

21.aes_alert_reset.44350326493252124525792635744195734623236474443643341201383208417909645417132
Line 3448, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/21.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 33311042 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 33271042 PS)
  UVM_ERROR @  33311042 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  33311042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 56.aes_core_fi.50833141180618255988578498264447375694491467172965998094839647640918100294160
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020408777 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020408777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```