AES/UNMASKED Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	242.459us	1	1	100.00
V1	smoke	aes_smoke	6.000s	263.533us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	132.968us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	64.097us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	199.412us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	75.924us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	108.248us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	64.097us	20	20	100.00
		aes_csr_aliasing	8.000s	75.924us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	263.533us	50	50	100.00
		aes_config_error	8.000s	518.906us	50	50	100.00
		aes_stress	7.000s	178.556us	50	50	100.00
V2	key_length	aes_smoke	6.000s	263.533us	50	50	100.00
		aes_config_error	8.000s	518.906us	50	50	100.00
		aes_stress	7.000s	178.556us	50	50	100.00
V2	back2back	aes_stress	7.000s	178.556us	50	50	100.00
		aes_b2b	9.000s	150.686us	50	50	100.00
V2	backpressure	aes_stress	7.000s	178.556us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	263.533us	50	50	100.00
		aes_config_error	8.000s	518.906us	50	50	100.00
		aes_stress	7.000s	178.556us	50	50	100.00
		aes_alert_reset	7.000s	321.489us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	66.746us	50	50	100.00
		aes_config_error	8.000s	518.906us	50	50	100.00
		aes_alert_reset	7.000s	321.489us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	176.472us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	173.810us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	321.489us	50	50	100.00
V2	stress	aes_stress	7.000s	178.556us	50	50	100.00
V2	sideload	aes_stress	7.000s	178.556us	50	50	100.00
		aes_sideload	6.000s	761.307us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	398.306us	50	50	100.00
V2	stress_all	aes_stress_all	38.000s	2.499ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	54.319us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	85.355us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	85.355us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	132.968us	5	5	100.00
		aes_csr_rw	7.000s	64.097us	20	20	100.00
		aes_csr_aliasing	8.000s	75.924us	5	5	100.00
		aes_same_csr_outstanding	7.000s	135.881us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	132.968us	5	5	100.00
		aes_csr_rw	7.000s	64.097us	20	20	100.00
		aes_csr_aliasing	8.000s	75.924us	5	5	100.00
		aes_same_csr_outstanding	7.000s	135.881us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	94.693us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	86.081us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	86.081us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	86.081us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	86.081us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	10.000s	167.417us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	2.804ms	5	5	100.00
		aes_tl_intg_err	10.000s	124.039us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	124.039us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	321.489us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	86.081us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	263.533us	50	50	100.00
		aes_stress	7.000s	178.556us	50	50	100.00
		aes_alert_reset	7.000s	321.489us	50	50	100.00
		aes_core_fi	33.000s	10.002ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	86.081us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	105.691us	50	50	100.00
		aes_stress	7.000s	178.556us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	178.556us	50	50	100.00
		aes_sideload	6.000s	761.307us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	105.691us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	105.691us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	105.691us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	105.691us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	105.691us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	178.556us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	178.556us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	143.537us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	165.918us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	143.537us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	37.000s	10.007ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	143.537us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_ctr_fi	6.000s	165.918us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	165.918us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	321.489us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	165.918us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
		aes_ctr_fi	6.000s	165.918us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_ctr_fi	6.000s	165.918us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	143.537us	49	50	98.00
		aes_control_fi	29.000s	10.004ms	272	300	90.67
		aes_cipher_fi	37.000s	10.007ms	329	350	94.00
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	20.000s	2.100ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.34	97.69	94.81	98.80	93.63	98.07	91.11	98.85	98.39

Failure Buckets

Job timed out after * minutes has 36 failures:
- Test aes_control_fi has 20 failures.
  - 3.aes_control_fi.105915790263879204710106834672439088125254603429098021199848137549001509238631
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 28.aes_control_fi.60029394924282787666249933077023491781598764115815764606124348773755389958462
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 16 failures.
  - 43.aes_cipher_fi.65762707832010899586804058091575018585678587666658559872733125610230066941066
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 47.aes_cipher_fi.22646197009113843249122233774845512103077344011802788602160782334635844905788
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 16.aes_control_fi.65028166390999986272036763616582181559227116208052645079687072008076837047244
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005008021 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005008021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 63.aes_control_fi.13523085926538409503254749568724323238331098895789469132128728643562265696118
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008516151 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008516151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.94813983514372776636680881554974278510805139659937658550344872773382551274385
Line 291, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 459658191 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 459658191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.4261194765774566129087120677142812003873347784756727912688358034413828813105
Line 593, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 187612304 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 187612304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 64.aes_cipher_fi.115222797754554082219274036045991145921518306422826393796668976253997064582765
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/64.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003978159 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003978159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 206.aes_cipher_fi.63007835840494012913127948626162376257825372920120025701193093335211774541799
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/206.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005005934 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005005934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.45235341179280296866850021994481104989710769337075785193237785225764445641139
    Line 150, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  54258065 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  54258065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.26196867241097031501269776335796405092006778135265625000540049320618047121773
    Line 194, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 695083389 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 695083389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 13.aes_core_fi.40840849757487763351884619038838796959560710949029823768919739259851971439605
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003746620 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003746620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 43.aes_core_fi.19903904521671368165674416340059417179596740403119953030913355228586922529199
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002468118 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002468118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:925) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.30425745373806580317447553940452011185284465491753327217873585475013921430099
    Line 168, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 311194634 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 311194634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.62722090526670464807012293003829995180495436386396727723284604583077786800013
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  23155823 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  23155823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

19.aes_fi.20001354485800525482620620105711356207245774326664836452447257609862279003437
Line 2328, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 25360918 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 25322456 PS)
  UVM_ERROR @  25360918 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  25360918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---